Floating-Point DSP Solutions

New digital signal processing (DSP) systems use floating-point solutions to achieve a high degree of numeric stability and dynamic range. Applications such as radar, advanced wireless antenna processing and medical imaging require floating-point capabilities in FPGAs and SoCs. As DSP applications grow in size and capability, FPGAs and SoCs offer the highest performing platforms available for any floating-point DSP implementation.

At 20 nm, Arria^® 10 FPGAs and Arria 10 SoCs deliver several key advantages for floating-point DSP implementation. Find out more about our Arria 10 FPGA and Arria 10 SoC variable-precision DSP block architecture.

Get started on our floating-point DSP solutions with these white papers and webcasts.

White Papers

		NEW: BDTI evaluates energy efficiency of real-world, complex DSP designs on Altera 28 nm development boards: Power benchmarks for complex DSP designs: Cholesky and QR-based matrix factorization Results and usability of the floating-point tool flow Read white paper (PDF)
		BDTI evaluates performance of real-world, complex DSP designs on Altera 28 nm development boards: Performance benchmarks for complex DSP designs: Cholesky and QR-based matrix factorization Results and usability of the floating-point tool flow Read white paper (PDF) Watch preview

Webcast: Implementing Floating-Point DSP in an FPGA
		View now, On-Demand, 30 minutes Learn how Altera^® FPGAs solve floating-point challenges See Altera's model-based tool flow using our DSP Builder Advanced Blockset and MATLAB and Simulink tools from MathWorks Get a third-party white paper from BDTI that analyzes our floating-point DSP design flow

Altera and MathWorks Joint Webcasts

Introduction to FPGA Design Using MATLAB and Simulink

Learn how many companies are reducing FPGA design cycle time by 33-50% or more by adopting workflows based on MATLAB and Simulink.

Watch webcast

Designing and Developing Pulse Doppler Radars Using FPGAs

Learn how radar system engineers can reduce the time required to model, simulate, and implement radar system designs and their constituent signal processing algorithms.