DSP IP Cores Overview Page
Altera’s digital signal processing (DSP) portfolio consists of proven, high-performance, standard algorithms and functions created to help engineers meet rapidly evolving technologies. All Altera® MegaCore® functions and megafunctions in the Altera Megafunction Partners Program (AMPPSM) have been rigorously tested to meet or exceed the exacting requirements of industry standards.
Complete Solution for the DSP Market
Altera provides an extensive portfolio of drop-in DSP functions, ranging in complexity from simple building blocks to complete end-market., application-specific solutions. Integrating your own library of proven, custom DSP functions with Altera supplied functions is push-button easy when using Altera's DSP Builder software utility capability.
DSP Builder shortens DSP design efforts by helping you create the hardware representation of a DSP design in an algorithm-friendly development environment (linking The MathWorks MATLAB and Simulink software with Altera's Quartus® II software).
Using SOPC Builder, DSP intellectual property (IP) can be integrated easily as hardware accelerators for a Nios® processor, or into the datapath as a pre- or post-processor to implement computationally rigorous routines. By leaving the digital signal processor at the center of the original design and adding a high-performance FPGA to free bottlenecks at both ends of a process, DSP software engineers are able to leverage existing software code while enjoying the benefits of hardware acceleration.
Reference Designs, Development Boards, IP Core Functions & More
Altera's IP MegaStore® provides details about DSP IP, reference designs, and development boards. You can also review Altera web pages for DSP Reference Designs and End Market Specific Reference Designs.
The following are DSP building block IP core functions offered by Altera, and you can find additional DSP functions by doing a keyword search using the IP MegaStore search engine.
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