Frequently Asked Questions—Embedded Processing
Using FPGAs in Embedded Systems
Q. How can I use an FPGA in my embedded design?
A. There are many ways to use FPGAs in an embedded system. Typical uses include:
- I/O and peripheral expansion—Add peripherals missing from your current processor such as LCD or memory controllers, or increase the number of I/O channels in your system by adding Ethernet, GPIO, or UART ports.
- Coprocessing—Boost system performance by moving compute-intensive algorithms from software running on a processor to hardware in the FPGA. Signal processing, image processing, and packet processing applications achieve orders of magnitude performance improvement running in hardware rather than software.
- Custom embedded controller—You decide which (and how many) processors, peripherals, interfaces, direct memory access (DMA) channels, and memories to include in your custom embedded controller.
- Multiprocessor—Accelerate your software development, improve code reliability, and increase maintainability by distributing tasks across several CPUs. You can design a multiprocessor system as a custom system inside a single FPGA or to augment an external CPU or digital signal processor.
Q. How can designing with FPGAs reduce risk in my embedded design?
A. FPGA developers enjoy several benefits not available to traditional embedded solutions:
- Protect your software investment from processor obsolescence—Because you own the hardware design for an FPGA-based embedded processor, your software investment is protected from processor obsolescence. In a worst case scenario, you can migrate your embedded design to a new FPGA family, requiring a board redesign. Your software investment, however, remains intact because the processor subsystem does not change. Learn more about protecting your software from processor obsolescence.
- Reduce time-to-market—By adding an FPGA to your design you can release new products earlier, with modest feature sets, and then upgrade the hardware over time. Altera provides an easy path to remotely update FPGA hardware designs over the Internet. In some cases, entire product lines can be based on a single board design; the variable content is contained within the FPGA. Learn more about reducing time-to-market and increasing productivity.
- Adapt to changing requirements—FPGAs let you adapt to last-minute changes or evolving standards by adding or changing hardware features even after the PCB is complete. Learn more about flexibility.
- Increase system performance without board redesign—Sometimes you discover late in the design process that the system doesn’t meet performance. By including an FPGA in the system, you can add more performance without having to redesign the board, purchase a faster speed-grade device, or re-write code in assembly. You can add multiple processors, custom instructions, and hardware accelerators to the FPGA to boost system performance without requiring a board redesign. Learn more about increasing performance.
Soft Processors
Q. What is a soft processor?
A. FPGA processors can be “hard” or “soft." Hard processors are implemented within the fixed silicon design on the FPGA, similar to discrete processors. On FPGAs, however, the CPU is surrounded by programmable logic (such as peripherals, memory interfaces, and so on) that you can configure to perform other functions. Hard processors typically offer higher CPU performance than soft processors, depending on factors such as processor architecture, clock rate, and process technology. As the name implies, hard processor performance and feature sets are fixed and typically offered only as a variation of a particular FPGA. The number and type of hard processors within an FPGA are also fixed as a function of that particular FPGA.
Soft processors, conversely, are implemented in programmable logic, use on-chip resources such as multipliers and memory, and can be instantiated in almost any FPGA family. The performance and cost of a soft processor depend mainly on the FPGA in which the processor is instantiated, but performance and cost are typically lower than in hard processor implementations. The number of soft processors that can be instantiated in a single device is limited only by the device’s resources (that is, its logic and memory). High-density FPGAs, for example, can contain hundreds of soft processors. Likewise, different types of soft processors can be implemented: 16- or 32-bit, performance optimized, logic-area optimized, and so on. You can choose to migrate your soft processor designs to hard processor implementations when moving to high-volume HardCopy® ASICs, gate arrays, or cell-based designs.
Nios II Embedded Processor
Q. What is the Nios II embedded processor?
A. The Nios II embedded soft processor is a general-purpose, 32-bit RISC CPU optimized for programmable logic. Three distinct processor cores provide maximum design flexibility, balancing system performance needs and logic element (LE) usage:
- Nios II/f (fast)—highest performance, moderate FPGA utilization
- Nios II/s (standard)—high performance, low FPGA utilization
- Nios II/e (economy)—modest performance, lowest FPGA utilization
Nios II processor architecture:
- 32-bit instruction set architecture
- 32-bit data and address paths
- 32 general-purpose registers
- 32 external interrupt sources
- Configurable instruction cache (/f and /s cores only)
- Configurable data cache (/f core only)
- Common interface for up to 256 custom instructions
- Up to four tightly coupled memories
Learn more about how customers are using the Nios II processor.
Learn more about Nios II processor cores.
Q. Who is using Nios II processors today?
A. With over 16,000 kits shipped and the world’s top 20 OEMs already using the Nios II processor, the Nios architecture is the most popular configurable soft processor available today. Learn more about how customers are using the Nios II processor.
Q. Which Altera® FPGA series support the Nios II processors?
A. Nios II processors are fully supported by the Stratix®, Cyclone®, and ArriaTM GX FPGA series.
Q. Can Nios II processors be implemented in HardCopy ASICs?
A. Yes. Systems built with Nios II processors can easily migrate from Altera's FPGAs to HardCopy ASICs to significantly reduce cost.
Q. How much performance does the Nios II processor deliver, and how much logic does it consume?
A. The performance and logic utilization of the Nios II processor depend heavily on the processor configuration and device family used. An online data sheet (PDF) provides benchmarks for various configurations and FPGA usage.
Q. What hardware development tools are provided for designing with the Nios II processor?
A. Altera provides a complete set of design tools for the Nios II processor:
- Intellectual property (IP) cores—In addition to the Nios II processor, a suite of embedded peripherals is provided, including UART, timer, memory controllers, serial peripheral interface (SPI), DMA, and more, from which you can design a custom embedded microcontroller. Learn more about commonly used IP and peripherals.
Nios II processor development kits also include a license for the Altera® DDR SDRAM controller. Learn more about the Altera DDR SDRAM Controller MegaCore® function.
- System-level design tools—Altera’s SOPC Builder system design tool lets you select the system components (that is, processor, peripherals, memories, and so on) from a comprehensive list of IP cores using a GUI. SOPC Builder generates the system interconnect logic automatically, outputs HDL files that define all components of the system and a top-level HDL design file that connects all the components together, and creates a system testbench. SOPC Builder also allows you to create your own reusable custom components and add them to the pool of available IP cores. Learn more about SOPC Builder.
- FPGA design software—Altera's Quartus® II design software provides a complete, multiplatform design environment for all phases of FPGA and CPLD design. Learn more about FPGA design flow.
- Embedded software development tools—The Nios II processor Embedded Development Suite (EDS) provides a complete set of design and debugging tools for the embedded software developer. Learn more about embedded software design tools.
All hardware and software components needed to design a Nios II processor-based system (Nios II processor EDS, IP, SOPC Builder system development tool, and Quartus II FPGA design software) are available for free download from the Altera website and are included in Altera’s development kits. Download Nios II design tools.
Q. Can I try the Nios II embedded processor (and tool chain) before I buy it?
A. Yes. You can download and design with the latest (fully functional) release of the Nios II embedded processor for free from the Altera website. However, before shipping a product containing a Nios II processor-based system you must purchase a license.
Q. What are custom instructions and how do they work?
A. Custom instructions are user-developed hardware blocks that extend the Nios II processor instruction set to accelerate software algorithms. Up to 256 custom instructions can be added per Nios II processor core. The Nios II processor software development tools automatically generate macros that can be called from within a C application and operate much like a C subroutine call, with zero overhead. Similar to native Nios II processor instructions, custom instruction logic can take values from up to two source registers and (optionally) write back a result to a destination register. A library of general-purpose and floating-point custom instructions are provided with the Nios II processor IP. Learn more about custom instructions.
Download the Nios II Custom Instruction User Guide (PDF).
Q. What are tightly coupled memories and how do they help?
A. A tightly-coupled memory is fast on-chip memory that bypasses the processor cache and has guaranteed low latency and provides the best memory access performance.
Download the Using Nios II Tightly Coupled Memory Tutorial (PDF).
Q. What is the system interconnect fabric?
A. The system interconnect fabric is a true, nonblocking interconnect automatically created by SOPC Builder that supports multiple simultaneous master-slave transactions and therefore delivers dramatic improvements in overall system performance compared to traditional shared media bus structures. The system interconnect fabric requires minimal FPGA resources and supports the following:
- Simultaneous multiple master operation
- Up to 4 Gbytes of address space
- Synchronous interface
- Built-in address decoding
- Read and write transfers with latency
- Streaming transactions
- Dynamically sized peripheral interface
- Multiple clock domains
- Pipelined operation
Learn more about the system interconnect fabric.
Download the Avalon® Memory-Mapped Interface Specification (PDF).
Q. What do I need to know to create my own peripherals to use with the Nios II processor?
A. The SOPC Builder system design tool includes a component editor that allows you to import your own intellectual property (IP) cores and package them as SOPC Builder components for design reuse. Once packaged, the component can include a GUI for IP parameterization generated automatically by the component editor, a user-provided software driver, and simulation testbench.
Learn more about the component editor (PDF).
Q. Can I remotely update my FPGA over Ethernet?
A. Yes, the ability to update firmware over Ethernet is a common feature in today's embedded systems. Using the Nios II processor, you can extend the capability to updating the hardware image of one or more FPGAs.
Learn more about remote configuration over Ethernet (PDF).
Q. Can multiple Nios II processor cores be implemented in a single FPGA?
A. Yes, many developers implement multiple Nios II processors on a single FPGA. Altera’s SOPC Builder system design software provides a drag-and-drop interface to add and connect multiple processors, shared memories, and hardware mutex and mailbox peripherals. The Nios II processor EDS supports software development and debug of multi-CPU designs. Several embedded partners also provide RTOS and debugging tools to enhance development of multi-CPU designs.
Learn more about using multiple processor cores (PDF).
Download a multiprocessor tutorial (PDF).
Q. What hardware debug tools are available for Nios II processor development?
A. There are several debug tools that accelerate hardware development:
- SignalTap® II embedded logic analyzer—The SignalTap II logic analyzer is a system-level debugging tool that captures and displays real-time signal behavior in a system-on-a-programmable-chip (SOPC), allowing you to observe interactions between hardware and software in system designs. Learn more about SignalTap II logic analyzer.
- FS2 FPGAView software for Tektronix logic analyzer—The First Silicon Solutions (FS2) FPGAView software is a PC Windows-based program designed for use with Tektronix TLA series logic analyzers to enable real-time debugging of Altera FPGAs. Using FPGAView, you can quickly and easily measure signals inside your Altera FPGA design and select different internal signals to probe without having to recompile your design. Learn more about FPGAView software.
Software Development Tools
Q. What software development tools are included with the Nios II processor?
A. A complete set of embedded software development tools including the Nios II Integrated Development Environment (IDE), compiler, debugger, instruction set simulator, device drivers, hardware abstraction layer API (PDF), flash programmer (PDF), and related utilities (PDF) are bundled together as the Nios II processor EDS. The Nios II processor EDS also contains the NicheStack TCP/IP network stack, Micrium MicroC/OS-II real-time operating system, and Nios II C-to-Hardware (C2H) acceleration compiler with free development licenses.
All hardware and software components needed to design a Nios II processor-based system (Nios II processor EDS, IP, SOPC Builder system development tool, and Quartus II design software) are available for free download from the Altera website and are included in Altera’s development kits. Download Nios II design tools.
Q. Which embedded software tool providers support the Nios II processor?
A. The Nios II processor is supported by several commercial OS, RTOS, debugger, middleware, and development tool providers. Learn more about software tools and software components.
Q. How do I develop software for a Nios II processor system?
A. The Nios II processor EDS collection of tools, utilities, libraries, and drivers contains everything needed to develop software applications for Nios II processor-based systems. The Nios II processor EDS includes:
All of these tools and libraries are included as part of the Nios II processor EDS, which is available for free download and included in all Nios II processor development kits.
Download Nios II design tools.
Q. What do I need to know to write applications using the Nios II processor HAL?
A. Reference designs demonstrating the use of the Nios II processor HAL routines are included with the Nios II processor EDS; documentation for using the Nios II processor HAL is available for download from Altera's website.
Learn about the HAL system library (PDF).
Download the HAL API Reference (PDF).
Q. What do I need to know to develop my own Nios II processor device drivers?
A. The Nios II processor EDS includes a library of peripheral device drivers. Documentation for creating your own device drivers is available for download from Altera's website.
Learn more about developing device drivers (PDF).
Q. What software utilities are included with the Nios II processor EDS?
A. In addition to the Nios II processor IDE, several command-line utilities come with the Nios II processor EDS to support project build, file conversion, download, debug, terminal, console, and GNU tool chain operations.
Learn more about development tools provided by Altera (PDF).
Q. What network support is provided for Nios II processor application development?
A. The Nios II processor EDS includes the NicheStack TCP/IP network stack, which is a small-footprint TCP/IP network stack providing IP, TCP, UDP, DHCP, ICMP, and ARP protocols using a standard sockets API.
Learn more about the NicheStack TCP/IP Network Stack - Nios II Edition (PDF).
Q. Which RTOS support is provided in the Nios II processor EDS?
A. The Nios II processor EDS includes reference designs, source code, and an evaluation license for the Micrium MicroC/OS-II RTOS.
Learn more about the MicroC/OS-II RTOS (PDF).
Q. What software tools are provided for developing interrupt service routines?
A. The Nios II processor HAL API provides facilities for developing custom interrupt service routines.
Download the HAL API Reference (PDF).
Q. What software tools are provided for managing memory caches?
A. The Nios II processor HAL API provides facilities for managing cache memories.
Learn more about cache and tightly coupled memory (PDF).
Q. Can I develop software for multiple Nios II CPUs in a single FPGA?
A. Yes. Multiprocessor software application development and debug are supported by the Nios II processor IDE and SOPC Builder.
Learn more about using multiple processor cores (PDF).
Download a multiprocessor tutorial (PDF).
Nios II Processor C-to-Hardware (C2H) Acceleration Compiler
Q. What is the Nios II processor C2H acceleration compiler?
A. The Altera Nios II processor C2H acceleration compiler is a productivity tool for Nios II processor software developers that can substantially increase the performance of embedded software by automatically converting performance-critical, ANSI C language subroutines into hardware accelerators and integrating them into FPGA-based Nios II processor subsystems.
Learn more about the Nios II processor C2H acceleration compiler.
Download a hardware acceleration white paper (PDF).
Q. What does “hardware accelerator” mean?
A. Hardware accelerators are dedicated blocks of logic that perform computational algorithms in hardware and are implemented in hardware description languages such as Verilog HDL or VHDL.
Learn more about hardware acceleration.
Q. How do I use the Nios II processor C2H acceleration compiler?
A. The Nios II processor C2H acceleration compiler is a plug-in to the Nios II processor IDE and works within the traditional software development flow. The typical design flow consists of the following:
- Profile the software performance to identify subroutines that take too long to complete.
- Highlight the subroutine name, right-click the mouse, and select Accelerate with the Nios II C2H compiler.
- Review the compiler results, optimize the C code, and repeat as needed.
Download the Optimizing Nios II C2H Compiler Results application note (PDF).
Download the Accelerating Nios II Systems with the C2H Compiler Tutorial (PDF).
See an application example of the Nios II C2H acceleration compiler (PDF).
Q. How can I benefit by using the Nios II processor C2H compiler?
A. You can increase system performance, reduce development time, and reduce power consumption:
- Increase system performance—The C2H compiler generates hardware accelerators that typically run one or more orders of magnitude faster than software implementations. In other words, hardware accelerators can perform more computations per clock cycle than sequentially executed software code.
- Reduce development time—By generating accelerators automatically, the Nios II processor C2H compiler eliminates the time-consuming process of developing acceleration logic by hand, reducing design time from weeks or months to hours or days.
- Reduce power consumption—Because hardware accelerators perform more work per clock than software equivalents, the processor clock frequency can remain low, consuming less power, reducing system cost with lower speed parts, and simplifying board design.
Q. Do I have to be a hardware engineer to use the Nios II processor C2H compiler?
A. No, the Nios II processor C2H compiler is a tool that converts ANSI C code to hardware and is specifically designed for software engineers; there is no need to learn hardware description languages like Verilog HDL or VHDL. However, understanding the embedded system hardware architecture can be very beneficial in helping optimize the C code to maximize performance.
Q. What kind of performance boost should I expect to get with the Nios II processor C2H compiler?
A. Performance results vary depending on several factors (including algorithm implementation and coding style); however, the Nios II processor C2H compiler typically delivers performance between 10 and 45 times greater than non-accelerated software.
Download the Optimizing Nios II C2H Compiler Results application note (PDF).
Q. How much logic does the Nios II processor C2H compiler generate?
A. There is a direct trade-off between performance boosts and increased logic usage. Many mathematical algorithms translate well into hardware on the FPGA. Logic generated by the Nios II processor C2H compiler is strongly dependant on the coding style of the input C functions.
Q. Can I add multiple accelerators to one design?
A. Yes, the only limit to the number of accelerators that you can add to a design is the capacity of the targeted FPGA. Practically speaking, there are generally only a few software subroutines that are the performance bottlenecks of the system and thus ideal candidates for acceleration.
Q. Can I try the Nios II processor C2H compiler before I buy it?
A. Yes. You can download and design with the latest (fully functional) release of the Nios II processor C2H compiler for free from the Altera website. However, you must purchase a license before shipping a product containing a Nios II processor C2H compiler-generated hardware accelerator. Learn more about licensing.
Q. Which ANSI-C constructs does the Nios II processor C2H compiler support?
A. The Nios II processor C2H compiler supports the ANSI-C standard, including all data types, operators, control-flow and looping constructs, macros, function calls, and pointer and array access.
Q. Are there any ANSI-C constructs that the Nios II processor C2H compiler does not support?
A. The initial release of the Nios II processor C2H compiler does not support floating-point operations, recursive routines, or GOTO/LABEL statements.
Q. If the Nios II processor C2H compiler can accelerate practically any ANSI C code, can it accelerate C library functions like printf()?
A. The Nios II processor C2H compiler can accelerate C library functions, but a better question is “what functions should it be used to accelerate?” The Nios II processor C2H compiler is designed for use in computationally challenged algorithms typically found in signal processing, image processing, and packet processing applications. Typical candidates include C subroutines that consist of tight loops that transform blocks (or streams) of data; in other words, code that can benefit from parallel access to memory and requires many CPU clock cycles to complete each calculation. These subroutines typically consist of dozens of lines of code, not thousands of lines of code.
Q. Will I have to rewrite my software to use the Nios II processor C2H compiler?
A. While you do not have to rewrite code to use the Nios II processor C2H compiler, legacy C software may not have been written in a way that most effectively translates to hardware. The Nios II processor C2H compiler converts any ANSI C software code to hardware, but results improve dramatically by following the recommended coding style usage guidelines.
Download the Optimizing Nios II C2H Compiler Results application note (PDF).
Q. Is the Nios II processor C2H compiler a general-purpose C-to-gates design tool?
A. No, Altera specifically designed the Nios II processor C2H compiler to accelerate user-selected Nios II processor C code functions. It is not intended to convert entire C code applications into hardware designs.
Q. Can I use the Nios II processor C2H compiler for processors other than the Nios II processors?
A. No, the tool currently supports only the Nios II processor.
Q. Which FPGA series does the Nios II processor C2H compiler support?
A. The Nios II processor C2H compiler supports the same devices as the Nios II processor: the Cyclone, Stratix, and Arria GX FPGA series, as well as HardCopy ASICs.
Q. Can I switch between the hardware or software implementations of the algorithms during development?
A. Yes, the Nios II processor IDE lets you easily add or remove functions from the Accelerated Functions view. Once a software routine has been selected for acceleration, you can still opt to run your applications using either the software or hardware implementations. You can use this feature to verify that the Nios II processor C2H compiler-generated hardware accelerator is functionally identical to the original software algorithm.
Q. Does the Nios II processor C2H compiler require me to have the Quartus II design software installed?
A. Yes. The Nios II processor C2H compiler generates register transfer level (RTL) code to replace certain software routines in an application. This RTL relies on the SOPC Builder tool for integration into the Nios II processor system. The Quartus II software is available for download.
Q. How do I get the Nios II processor C2H compiler?
A. The Nios II processor C2H compiler is an integrated plug-in to the Nios II processor IDE. The Nios II processor IDE is included with the Nios II processor Embedded Design Suite, which ships with all Nios II processor development kits and the Quartus II design software. It is available for download here.
Product Availability and Licensing
Q. How do I get the Nios II processor and tools?
A. There are several ways to get the Nios II processor and development tools:
- Download from the Altera website
- Included with the Altera software subscription (DVD)
- Purchase a Nios II processor development kit
You can design, compile, and generate time-limited Nios II processor systems and hardware accelerators generated by the Nios II processor C2H compiler without obtaining a license file by using the OpenCore Plus evaluation feature. You must obtain a license for the Nios II processor core and the Nios II processor C2H compiler to generate non-time-limited programming files and flash programming files for new Nios II processor hardware systems. You do not need a license if you are only developing software using the Nios II processor IDE.
Q. What is the OpenCore Plus evaluation feature and how does it work?
A. If you download an Altera IP core (such as the Nios II processor) and do not already have the associated IP license, any designs you create operate in Altera’s OpenCore Plus evaluation mode and allow you to do the following:
- Simulate the behavior of the Nios II processor IP within your system
- Verify the functionality of your design, as well as evaluate its size and speed quickly and easily
- Generate time-limited device programming files for designs that include a Nios II processor
- Program a device and verify your design in hardware
OpenCore Plus hardware evaluation supports the following two modes of operation:
- Tethered—requires a JTAG connection between your board and the host computer. If tethered mode is supported by all megafunctions in a design, the device can operate for a longer time or indefinitely
- Untethered—the design runs for a limited time
Learn more about OpenCore Plus evaluation (PDF).
Q. What products are included with the Nios II processor and which require a license?
A. Refer to Table 1.
Note:
- License sold separately.
Q. Do I need to purchase any licenses before I can begin development?
A. No. You can use all the Nios II processor licensed products for development; there are no restrictions other than the untethered time-limited operation.
Q. How do I obtain a license for the Nios II processor and related products?
- Nios II Processor IP—To obtain a license file for the Nios II processor, non-time-limited use, you must purchase a Nios II processor development kit or the stand-alone Nios II processor core license (ordering code: IP-NIOS). Contact your local Altera representative or Altera Tools Support to order today.
- Nios II Processor C2H Compiler—To obtain licenses for the Nios II processor C2H compiler (ordering code: IPT-C2H-NIOS) contact your local Altera representative or Altera Tools Support to order today.
- NicheStack TCP/IP Network Stack - Nios II Edition—To obtain licenses for the NicheStack TCP/IP Network Stack, Nios II Edition, (ordering code: IPSW-TCPIP-NIOS) contact your local Altera representative or Altera Tools Support to order today.
- Micrium MicroC/OS-II RTOS—To obtain a license for the Micrium MicroC/OS-II RTOS, contact Micrium today.
Q. What do the Nios II processor product licenses entitle me to do?
- Nios II Processor IP—Once you purchase a Nios II processor license, you receive a perpetual, royalty-free license to ship systems that contain one or more Nios II processors targeted to Altera’s Cyclone, Stratix, or Arria GX series FPGAs or HardCopy series ASICs. The license also includes 1 year of updates to the product. You can purchase additional 12 month maintenance subscriptions to ensure you always have the latest release.
- Nios II processor C2H Compiler—Once you purchase a Nios II processor C2H compiler license you receive a perpetual, royalty-free license to ship systems that contain one or more C2H compiler-generated hardware accelerators targeted to Altera’s Cyclone or Stratix series FPGAs or HardCopy series ASICs (a Nios II processor license is also required). The license also includes 1 year of updates to the product. You can purchase additional 12-month maintenance subscriptions to ensure you always have the latest release.
- NicheStack TCP/IP Network Stack - Nios II Edition—Once you purchase a NicheStack TCP/IP network you receive a perpetual, royalty-free license to ship systems that contain software based on the NicheStack source code targeted to the Nios II processor running in Altera’s Cyclone, Stratix, or Arria GX series FPGAs or HardCopy series ASICs. The license also includes 1 year of updates to the product. You can purchase additional 12-month maintenance subscriptions to ensure you always have the latest release.
- Micrium MicroC/OS-II RTOS—Contact Micrium for license details.
Q. Do I need to purchase a Nios II processor license to use the Nios II processor C2H compiler?
A. You must have an active Nios II processor subscription to license the Nios II processor C2H compiler.
Q. Can I get multiple Nios II processor licenses for our license server?
A. Yes, just as with any other Altera IP product, you may purchase as many license seats as you desire by using the IP-NIOS ordering code in conjunction with a FLOAT license for the Quartus II software. These seats are listed at $495 each, but bulk and corporate discounts are negotiable. Contact customer service for details.
Q. Does Altera offer a Nios II processor license for ASIC development?
A. Yes. An ASIC license is available for Nios II processors. An ASIC optimized version of the Nios II processor core is available from the Synopsys DesignWare STAR IP program. Please contact your Altera sales representative for details.
Training and Technical Resources
Q. What training is available for Nios II processor developers?
A. Currently there are several training resources available:
- Online training—Several training modules are available for free from the Altera training website. Learn more about training resources.
- Instructor-led training—Altera provides training classes at many locations around the world. Learn more about training resources.
- Tutorials—Altera’s Nios II processor development kits include several tutorials and related reference designs. These tutorials are also available for download from the Nios II Literature web page.
- Demonstrations on demand—While these modules are not intended as training, they provide a great overview of the design flow and tools used to develop Nios II processor systems. See online demonstrations.
Q. Are application-specific reference designs available?
A. Yes. There are several embedded reference designs posted on the Altera website to address specific applications such as image processing.
See reference designs.
See design examples.
Q. What Nios II processor documentation is available and how can I get it?
A. The best place to find the latest Nios II processor documentation is on the Nios Literature web page or search Altera.com for technical documentation.
Q. What other technical resources are available for Nios developers?
A. There is a wealth of information on the web to help you learn more about designing with the Nios II processor:
- Nios Forum—The Nios Forum is a community of over 6000 Nios processor developers worldwide who share ideas, challenges, and reference designs.
- Nios Wiki—The Nios Wiki provides a community resource where developers can post and maintain documentation and reference designs.
- Nios Design Contest Winning Papers—This website contains the winning white papers from the annual Nios II processor design contest. It contains dozens of white papers on reference designs using the Nios II processor in applications with topics ranging from communications to robotics.
Getting Started
Q. How hard is it to get started?
A. Getting started is simple. Learn more at our getting started page. Altera also provides development kits that contain an Altera FPGA and all the hardware and software necessary to begin your design. It takes about an hour from receiving the box to running your first program on the Nios II processor. Most of the time required is for software installation.
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