Scale System Performance
Altera’s Nios® II processors let you take full advantage of the inherent parallelism of FPGAs to achieve high levels of system performance. Multiple processors can execute code simultaneously while hardware accelerators can offload compute-intensive algorithms at the same time. Upgrade your embedded system’s performance at any stage of the product life cycle without the need to redesign the board or develop hand-optimized assembly code.
There are several ways to upgrade system performance:
Soft Processor Cores
Choose from three code-compatible soft processor cores (see Figure 1): one optimized for maximum system performance, one optimized for minimum logic usage, and one that strikes a balance between the two. You can easily configure these cores with features such as multipliers, user-specified cache memories, custom instructions, hardware debug logic, and more to adapt to your specific performance needs.
Figure 1. Nios II Processor Core Performance
Custom Instructions
Accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. You can add up to 256 custom instructions to each processor core to reduce the number of clock cycles required for numeric calculations, bit manipulation, and other complex processing algorithms (see Figure 2).
Figure 2. Custom Instruction Logic
Seventech
"The combination of Altera's Cyclone FPGA and Nios II processor was ideal for performing the image and audio processing in our Merlin embedded industrial controller. This was our first FPGA-based soft core microprocessor design, but we found the Nios II development environment to be easy to use and very powerful, enabling us to complete our project in less than six months. The ability to develop custom instructions for the Nios II processor allowed us to transcend the limitations of traditional embedded architectures and offer our customers a truly unique solution."
Salvo De Luca
Hardware and HDL Lead Designer
See how customers are using the Nios II processor
Hardware Accelerators
Automatically accelerate your software by converting C language subroutines into hardware accelerators that boost performance without increasing clock frequency and power consumption. Simply “right-click to accelerate” performance-critical functions using the Nios II C-to-hardware (C2H) acceleration compiler and eliminate the time and expense of manually generating Verilog or VHDL accelerators (see Figure 3).
Figure 3. Hardware Acceleration Example
Configurable Caches and Tightly Coupled Memory
Adjust the size of the processor instruction or data cache to meet the performance needs of your application. For fast access to frequently used routines, add up to four tightly coupled memories that provide cache-like access without the penalty of cache misses.
Multiprocessor Systems
Use multiple processors to scale your system's performance or to partition software applications into smaller, simpler tasks that are easier to write, debug, and maintain. The Nios II Embedded Design Suite (EDS) and tools from industry-leading embedded software providers support developing and debugging multiprocessor applications. Nios II processors, combined with high-density devices such as the Stratix® family of FPGAs and HardCopy® ASICs, are ideal platforms for creating high-performance multiprocessor systems (see Figure 4).
Figure 4. Multiprocessor Example
High-Bandwidth System Interconnect
Altera’s SOPC Builder system design software lets you generate high-throughput systems that take advantage of the inherent parallelism of FPGAs. The system interconnect fabric is fully switched, in that dedicated connections between master and slave components allow multiple simultaneous transactions without the arbitration stalls found in traditional bus architectures. Unburden your processor by using intelligent direct memory access (DMA) channels.
Other Benefits
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