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Transceiver Portfolio

Home > Technology > Transceivers

Related Links

  • View Stratix IV GT FPGA webcast
  • View Arria II GX FPGA webcasts
  • Download Software

Altera provides the industry’s broadest portfolio of 40-nm and 60-nm FPGAs and ASICs with integrated transceivers. Within this portfolio, you’ll discover a diverse mix of power, performance, densities, and prices to match your specific design requirements. The portfolio is built on a common transceiver architecture and supported in a single suite of design tools. Quartus® II software, with more than 50 intellectual property (IP) cores, delivers the “learn it once, use it everywhere” productivity leverage required to sustain a competitive advantage in this market environment.

Building on more than 10 years of transceiver design, field support, and applications development, the Altera® 40-nm and 60-nm transceiver portfolio provides an array of capabilities.

  • Transceiver speeds from 155 Mbps to 11.3 Gbps
  • Density ranges from 15K logic elements (LEs) to 530K LEs and 11.5 million ASIC gates
  • Popular industry-standard transceiver protocols 
  • Low simultaneous switching noise (SSN) and superior eye quality

Table 1 provides information on Altera's portfolio of custom logic devices with integrated transceivers.

Table 1. Custom Logic Devices with Transceivers 
Device LEs Transceiver
Specifications
Memory (Mbits) Multipliers
(18 x 18)
I/O Pins
40-nm Stratix® IV GX FPGAs 70K–530K

0–16 at 3.75 Gbps

8–32 at 8.5 Gbps

6.3–20.3 384–1,024 288–904
40-nm Stratix IV GT FPGAs 230K–530K

12–24 at 11.3 Gbps

12-24 at 6.375 Gbps

13.9–20.3 1,024–1,288 636–754
40-nm Arria® II GX FPGAs 45K–256K 16 at 3.75 Gbps 1–11.8 48–1,288 150–600
40-nm HardCopy® IV GX ASICs 2.5M–11.5M
usable ASIC gates
8–36, up to 6.5 Gbps 6.3–20.3 384–1,288 368–736
60-nm Cyclone® IV GX FPGAs  15K-149K 2-8, up to 3.125 Gbps 0.5-6.5 0-360 72-475

Figure 1 shows examples of the Ethernet and PCI Express (PCIe) ranges for each device.

Figure 1. Example Ethernet and PCIe Capability Range Offered Through the 40-nm and 60-nm Transceiver Portfolio

Figure 1.Transceiver Portfolio Chart

Common Transceiver Architecture

All of the custom logic devices in our 40-nm and 60-nm portfolio use a proven, common transceiver architecture (see Figure 2).

Figure 2. Common Transceiver Block Architecture

Figure 2. Transceiver Block Diagram

  • Physical Coding Sublayer: PCS
  • Physical Medium Attachment: PMA

The portfolio also offers the productivity advantage of the comprehensive Quartus II design software, a common set of IP cores, and a variety of supporting reference designs and design examples. Learn the software once, then extend your skills across multiple design platforms.

With the device and Quartus II design software, you’ll experience:

  • Faster design and compile times
  • More efficient system resource utilization resulting in higher system integration
  • Higher integration with higher density products
  • Optimized core performance, so you can efficiently close timing on designs and lower your engineering costs
  • The ability to seamlessly connect IP blocks with a simple, intuitive GUI

Related Transceiver links

  • Altera's 40-nm transceiver FPGAs and ASICs brochure (PDF)
  • Altera product catalog (PDF)
  • Stratix IV GT FPGAs 
  • Arria II GX FPGAs
  • Transceiver protocols
  • Stratix IV GX FPGAs
  • HardCopy IV GX ASICs
  • Cyclone IV GX FPGAs
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