- 10-Gbps Ethernet Reference Design
- MorethanIP 10-Gigabit Ethernet IP Cores
- Hardware Validation (PCI Express Development Kit, Stratix II GX Edition)
- Stratix IV GX FPGAs
- Stratix IV GT FPGAs
- Stratix II GX FPGAs
- Arria Series FPGAs
- Cyclone IV GX FPGAs
- HardCopy IV GX ASICs
Altera provides a complete IEEE 802.3ae-2002 Ethernet standard-compliant Media Access Controller (MAC) and PHY FPGA-based or HardCopy® ASIC-based solution for a variety of chip-to-chip, backplane, and cable applications using the XAUI (10GBase-X and XGXS) interface protocol. The XAUI solution includes Altera® devices with integrated transceivers, development kits, intellectual property (IP) from Altera and MorethanIP, collateral, and test data. The solution enables simple, fast protocol implementation, which reduces design risk, shortens development times, and allows you to concentrate on the core functions of the system design.
Stratix® IV (GX and GT), Cyclone IV GX (EPC4GX50 and larger devices), Stratix II GX, and Arria® series FPGAs and HardCopy IV GX ASICs provide a fully integrated XAUI solution for high-performance applications. This solution is compliant with the IEEE 802.3ae standard and has been tested and validated successfully at the University of New Hampshire Interoperability Lab (UNH-IOL). It utilizes built-in transceivers to implement the XAUI protocol in a single device. Table 1 provides an overview of the complete XAUI solution.
| Table 1. Complete XAUI Solution | |
| Solution | Description |
|---|---|
| Transceiver | Integrated XAUI-compliant transceivers arranged in blocks |
| Supported Data Rates | 3.125 Gbps, 3.75 Gbps |
| Altera IP Reference Design | Altera 10-Gbps Ethernet reference design |
| Partner IP Core | MorethanIP 10-Gigabit Ethernet IP cores |
| Development Boards | PCI Express Development Kit, Stratix II GX Edition Stratix IV GX FPGA Development Kit Arria II GX FPGA Development Kit |
| Reference Designs | 10-Gbps Ethernet Hardware Demonstration Reference Design 10-Gbps Ethernet Loopback Reference Design |
| UNH XAUI Test & Interop Reports | Contact your local Altera sales representative |
| XAUI Characterization Report | Contact your local Altera sales representative |
Technology Background
Altera's Stratix IV (GX and GT), Cyclone IV GX, Stratix II GX, Arria series, and HardCopy IV GX devices are equipped with built-in transceivers that provide a dedicated mode for implementing the XAUI interface and allow the integration of multiple 10-Gbps Ethernet PHYs and MACs into a single device. Embedded within the transceivers are dedicated rate-matching and clock compensation FIFO buffers, 8B/10B encoders and decoders, and word-alignment functions, all controlled by dedicated XAUI state machines. Each group of four channels also has built-in channel alignment circuitry to minimize skew across the XAUI interface from XAUI source to sink. Figure 1 shows the 10-Gigabit Ethernet MAC with integrated physical coding sub-layer (PCS) block diagram interfacing with various 10-Gbps PHY devices and pluggable module options.
Figure 1. 10-Gigabit Ethernet MAC with Integrated PCS Block Diagram
Notes:
- SPI = serial peripheral interface
- SFP = small form-factor pluggable module
- MDIO = optional management data interface
- XFP = 10-Gigabit small form factor pluggable module
- XFI = 10-Gbps serial electrical interface
- SFP+ = 8.5 and 10-Gigabit per second small form-factor pluggable module
- SFI = SFP+ high-speed serial electrical interface
The transceiver module in Stratix IV (GX and GT), Cyclone IV GX (EP4CGX50 and larger devices), HardCopy IV GX, Arria II GX, Stratix II GX, and Arria GX devices meets all IEEE 802.3ae specifications, including jitter generation under 0.35 unit interval (UI) without pre-emphasis and jitter tolerance of more than 0.60 UI, peak-to-peak total. The transceiver module matches the IEEE 802.3 sinusoidal jitter-tolerance mask requirement. The 3.125-Gbps x4 channel unidirectional data transfer rate for 10-Gigabit Ethernet complies with the IEEE 802.3ae XAUI definitions for linking physical-layer devices with upper-layer devices.
The XAUI transceiver module provides a 156.25-MHz input reference clock and parallel interface along with a 4-channel clock data recovery (CDR) receiver and 4-channel transceiver arrays, an AC-coupled differential interface, and differential PCML drivers. The transceiver module also incorporates a 1:16 serializer/deserializer (SERDES) with a 16:20 gearbox, 8B/10B coding, and lane alignment. The transceivers offer up to 500 percent pre-emphasis and up to 17-dB equalization to compensate high-frequency losses.
Altera offers an array of silicon-proven 10-Gigabit MAC cores with built-in support for the XGMII, XAUI, XSBI (64B/66B PCS layer) interfaces, and OC-192. Built-in support is also provided for flow control, MII management, address-based filtering, and statistics counters for RMON and SNMP. The 10-Gigabit Ethernet MAC layer and reconciliation sub-layer core is compliant with the IEEE 802.3ae specification and supports multiple custom switch fabric enhancements to interface Altera's devices with 3.125-Gbps serial transceivers directly to several 10-Gigabit Ethernet switch devices.
Altera is the first FPGA vendor to deliver a multi-gigabit and 10-Gigabit Ethernet PCI Express host adapter card development kit. The host bus adapter, called the Stratix IV GX Development Kit, is built with Altera's Stratix IV GX EP4SGX230 FPGA, with up to 36 multi-gigabit transceivers accelerating the convergence of network and storage applications using 10-Gigabit Ethernet technology.
Ethernet is by far the most popular LAN technology expanding into the metro and WAN networks, and it is the dominant wired networking protocol. It has evolved from a 1-MHz shared medium signal running on coaxial cable to the present availability of numerous variants operating as fast as 10 Gbps. Altera's 10-Gigabit Ethernet solutions provide top-of-the-line performance for leading-edge network development.
