Altera and its intellectual property (IP) partners provide a complete solution to maximize system performance and design productivity based on 40/100 Gigabit Ethernet (GbE) media access controller (MAC), physical coding sublayer (PCS), and physical media attachment sublayer (PMA) with 40 Gbps or 100 Gbps Attachment Unit Interface (XLAUI or CAUI) designed to the latest IEEE 802.3ba 40/100 GbE standard. This solution can be used for a variety of chip-to-optical module, chip-to-chip, and backplane applications. Altera® Arria® 10, Stratix® V GT, and GX FPGAs with transceivers at data rates up to 28.05 Gbps or 14.1 Gbps, and Stratix IV GT FPGAs with data rates up to 11.3 Gbps implement XLAUI or CAUI electrical interfaces with 4 or 10 fully integrated and silicon-proven 10.3125 Gbps serial transceivers, respectively, to connect to standard CFP optical modules. Altera 100GbE IP in Stratix V GT FPGA also supports CAUI-4 (4 x 25.7 Gbps) interface to interface to CFP2 optical modules.
In addition to the FPGAs, our 40/100 GbE solution also includes development kits, IP from Altera and MorethanIP, collateral, and test data.
The 40GBASE-R and 100GBASE-R PMAs have been tested in hardware, and the complete MAC and PHY solution has been verified. The 40/100 GbE PHY utilizes built-in transceivers to implement the XLAUI and CAUI interface specifications in a single device, which saves the system cost, board space, and the power of external serializer/deserializer (SERDES) devices. Table 1 provides an overview of the complete 40/100 GbE solution in Altera devices.
|Table 1. Complete 40/100 GbE with XLAUI and CAUI Interface Solution|
|Transceiver||Integrated 10.3125 Gbps transceivers arranged in blocks|
|Supported data rates||10.3125 Gbps per serial channel, 4 x 10.3125 Gbps and 10 x 10.3125 Gbps|
|Stratix IV GT or Stratix V GX FPGA XLAUI-CAUI characterization report||Contact your local Altera sales representative|
Altera's Arria 10, Stratix V GT, and GX FPGAs, and Stratix IV GT FPGAs have built-in serial transceivers to implement the 40/100 GbE PMA (40GBASE-R and 100GBASE-R) with a XLAUI or CAUI interface. These FPGAs implement IEEE 802.3ba 40/100 GbE 40GBASE-R or 100GBASE-R PCS with soft IP in the FPGA fabric. These devices allow the integration of 40/100 GbE MAC and PHY into a single device for optimal system design. Some Stratix IV GT FPGAs only support 40GbE interfaces.
Figure 1 shows the complete 40/100 GbE MAC and PHY solution interfacing to various 40-/100-Gbps external PHY devices. The external interface can also connect to another chip, and the Stratix V FPGA can also connect directly to a 40GbE (40GBASE-KR4) backplane or a 100 Gbps backplane.
The 40/100 GbE PHY function consists of two major functions: PCS (soft IP) and PMA integrated hard IP and management logic soft IP (not shown). The PHY can operate at full wire speed. The 40/100 GbE PCS transmitter consists of 64b/66b encoder, X58 scrambler, multi-lane (4 or 20 respectively for 40 Gbps or 100 Gbps) data distributor (inverse multiplexer), alignment block insertion, 66b/32b or 66b/40b gearbox in 40 Gbps PCS, and 66b/16b or 66b/20b gearbox in 100 Gbps PCS. The 4 or 10 lanes in the PMA operate at 10.3125 Gbps in unbonded mode and use adjacent serial transceivers in the device. PRBS-31 generator and checker in the PCS and local loopback from transmitter to receiver in the PMA allow system diagnostics testing.
The 40/100 GbE PCS receiver consists of phase compensation FIFO, gearbox, word-aligner, 4 or 10 physical to 4 or 20 virtual lane de-multiplexer, alignment block detection and removal, 4 or 20 lane deskew, re-order, and multi-lane alignment, 4 or 20 lane multiplexer, bit-error rate (BER) detector and monitor, X58 descrambler, 64b/66b decoder, optional receiver rate-matching and clock compensation FIFO buffer, and link up detection function.
The 40/100 GbE MAC supports full-duplex operations. Its functions support Ethernet frame encapsulation and decapsulation, automatic short frame pad insertion and removal, deficit idle count, reconciliation sublayer with link fault detection and reporting, Ethernet flow control, error detection and reporting, statistics counters, and management data input/output (MDIO) for CFP module management.
Figure 1. 40/100 GbE MAC and PHY with Serial 4/10 x 10-Gbps XLAUI or CAUI Interface Block Diagram
- CFP = 100-Gbps pluggable module
- MDIO = management data interface
- XLAUI = 40 GbE (4 x 10.3125-Gbps) Attachment Unit Interface (electrical interface)
- CAUI = 100 GbE (10 x 10.3125-Gbps) Attachment Unit Interface (electrical interface)
Figure 2 shows a sample application of the 40/100 GbE MAC and PHY in a high-performance switch or router network line card. In this example design, the Altera FPGA implements an integrated 40 or 100 GbE MAC chip with Interlaken interface. Then, the packet processor and traffic manager on the board processes the packets and transfers them to a switch fabric card over a backplane.
Figure 2. Switch or Router Line Card with 40/100 GbE MAC and PHY with XLAUI or CAUI Interface
Figure 3 shows an application example of a 40/100 GbE to optical transport node OTN4 (100 Gbps) transponder system. In this design, the Altera FPGA terminates a 40/100 GbE client port with a MAC and PHY, maps the Ethernet frames to Optical-Channel Data Unit ODU4, and vice versa. An OTN4 framer sends and receives the data to and from an external forward error correction (FEC) device via SFI-S interface (N x up to 11.3 Gbps). The data is then processed by FEC and sent out by the 100 Gbps optical module to the OTN4 network.
Figure 3. OTN4 Transponder Card with 40/100 GbE MAC and PHY with XLAUI or CAUI Interface
The transceiver modules in Arria 10, Stratix IV GT, and Stratix V FPGAs a with 40/100 GbE PHY are designed to the latest IEEE 802.3ba 40/100 Gbps Ethernet standard specifications, which includes the functions, electrical interface specifications, jitter generation, jitter tolerance, inter-lane skew, clock frequency variations (+/- 100ppm) and delay constraints.
The 40/100 Gbps PHY in the Stratix IV GT FPGA can operate with a 322.265625 MHz or 644.53125 MHz input reference clock. In the transceiver-based Stratix V FPGA, it can operate with a wider range of input reference clocks. This PHY provides 4 or 10 clock data recovery (CDR) receivers and 4 or 10 x 10.3125 Gbps data serial transceivers with AC-coupled differential interfaces and differential PCML drivers. The 40-/100 Gbps PHY internal parallel interface to MAC is XLGMII or CGMII.
Ethernet is the most popular LAN technology expanding into the metro and WAN networks, and it is the dominant wired networking protocol. Altera's 40/100 GbE solution provides top-of-the-line performance and high system integration for leading-edge network equipment development.
- Stratix V GT and GX FPGAs
- Stratix IV GT FPGAs
- 40 Gbps and 100 Gbps Ethernet MegaCore Function
- IEEE 802.3 Ethernet standards home page
- AN 570: Implementing the 40G/100G Ethernet Protocol in Stratix IV Devices (PDF)
- AN 572: Implementing the Scalable SERDES Framer Interface (SFI-S) Protocol in Stratix IV GT Devices (PDF)
- AN 573: Implementing the Interlaken Protocol in Stratix IV Transceivers (PDF)