Gigabit Ethernet

Altera provides a range of complete solutions to accelerate design cycles for devices that use IEEE 802.3 standard compliant Gigabit Ethernet ports for chip-to-chip, board-to-board, or backplane interconnects. Altera offers solutions for use within embedded systems or for networking over copper or fiber optic media. The solutions enable simple and fast protocol implementation to reduce design risk, shorten development times, and allow you to concentrate on the core functions of the system design.

Gigabit Ethernet Integrated Solutions

These Altera^® devices provide a fully integrated Gigabit Ethernet solution with a serial interface at 1.25 Gbps:

With integrated gigabit serial transceiver support
- Stratix^® IV GX FPGAs
- Stratix II GX FPGAs
- Arria^® series FPGAs
- Cyclone^® IV GX FPGAs
- HardCopy^® IV GX ASICs
With LVDS I/Os, integrated dynamic phase alignment (DPA), and soft-clock data recovery (CDR) mode support
- Stratix IV (E, GX, and GT) FPGAs
- Stratix III FPGAs
- HardCopy IV (E and GX) ASICs
- HardCopy III ASICs

The embedded transceivers in Stratix IV GX, Stratix II GX, Cyclone IV GX, Arria series, and HardCopy IV GX devices fully support IEEE 802.3 Gigabit Ethernet (GbE) physical coding sublayer (PCS) and physical medium attachment (PMA) layers of the protocol. The LVDS I/Os (at 1.25 Gbps) with integrated DPA and soft-CDR mode of Stratix IV, Stratix III, HardCopy IV, and HardCopy III devices fully support IEEE 802.3 1000Base-X (1GbE) PMA layer of the protocol and SGMII specifications. These integrated functions, combined with Altera’s Triple-Speed (10/100/1000 Mbps) Ethernet MegaCore^® function, allow the complete protocol to be implemented in a single device.

Altera's Triple Speed Ethernet MegaCore function and the integrated PMA and PCS, and soft PCS IP, have successfully passed the University of New Hampshire Interoperability Lab (UNH-IOL) 10/100-Mbps and 1-Gbps Ethernet MAC and PCS validation tests with Stratix II GX and Stratix II FPGAs.

Altera devices do not directly interface to 10Base-T (10 Mbit over unshielded twisted pair copper cable), 100Base-T (100 Mbit over copper), and 1000Base-T (1 Gbit over copper) networks. Therefore, Altera devices need an external 10/100/1000Base-T standard PHY device for connection to the Ethernet copper cable.

Table 1 gives an overview of the complete Gigabit Ethernet solution.

Solution	Description
*Table 1. Complete Gigabit Ethernet Solution with Integrated Serial Interface*
Device	Stratix IV FPGAs Stratix III FPGAs Stratix II GX FPGAs Arria series FPGAs Cyclone IV GX FPGAs HardCopy IV ASICs HardCopy III ASICs
Physical Interface	Integrated PHY providing full PMA and PCS support
Gigabit Ethernet IP Core	Gigabit Ethernet IP cores
Development Boards	Stratix IV GX FPGA Development Kit Arria II GX FPGA Development Kit PCI Express Development Kit, Stratix II GX Edition Arria GX FPGA Development Kit 10/100/1000 Quad PHY HSMC Daughter Board from MorethanIP SFP HSMC Board (8-port 10/100/1000 Mb Ethernet SFP from Terasic Technologies, Inc.)
10/100/1000Mb Ethernet UNH Test Report	Contact your local Altera sales representative
Gigabit Ethernet Characterization Report	Contact your local Altera sales representative

External Transceiver Solutions

Some Altera devices only provide parallel external interface for Gigabit Ethernet, so they need an external standard Ethernet PHY device with a parallel interface to the MAC/PCS. Table 2 shows the GbE solutions with Altera devices that only have a parallel interface to an external transceiver or PHY device. Connectivity between these Altera devices and the external PHY device is via an industry-standard GMII or RGMII interface for MAC or TBI interface for PCS.

Solution	Description
*Table 2. Gigabit Ethernet Solutions with External Serial Transceiver Device*
Devices	For high-volume and cost-sensitive applications: Cyclone IV E FPGAs Cyclone III FPGAs Cyclone II FPGAs For high-density and performance applications: Stratix II FPGAs HardCopy II ASICs
Physical Interface	These devices support Gigabit Ethernet MAC ports with a GMII or RGMII interface and an external transceiver, or the PCS ports with TBI interface
Gigabit Ethernet IP Core	Gigabit Ethernet IP cores
Development Board	Nios^® II Development Kit, Cyclone II Edition and Nios II Development Kit, Stratix II Edition with MorethanIP 10/100/1000 Ethernet PHY Daughterboard with Marvell PHY

Technology Background

Ethernet was originally defined as a LAN technology to interconnect client PCs at line rates of 10 Mbps through hubs and, later, switches. Over the years, client line rates increased to 100 Mbps (Fast Ethernet) and 1 Gbps. Switches aggregating multiple 10/100Mb lines to 1-Gbit uplinks and later aggregating multiple 1-Gbit lines to 10-Gbit uplinks emerged as network bandwidth demand grew and new applications emerged. The near ubiquitous use of Ethernet technologies in LANs has resulted in significant economies of scale, driving down the component costs, including the switch devices.

Today, Gigabit Ethernet is a cost-effective technology when used to do the following:

Connect multiple devices to a local CPU
Interconnect multiple boards across a backplane or across systems for data transfer
Control signaling between line cards and the host CPU within an embedded system

Figure 1 shows a Gigabit Ethernet high port count line card using an Altera Stratix III or Stratix IV FPGA for multi-port MAC front end function and an FPGA for backplane interconnect. These FPGAs include the Triple Speed Ethernet MegaCore function for high-performance data plane and for control signaling (control plane) to the host CPU.

Figure 1. Gigabit Ethernet MAC in Data Plane and Control Plane Applications

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Gigabit Ethernet