HyperTransport™ technology is a high-speed protocol for use in connecting peripherals to computers, mobile computers, servers, communication systems, network equipment, and embedded equipment. It provides up to 128-Gbps aggregate bandwidth, and can be configured with 2-, 4-, 8-, 16-, or 32-bit buses. It is intended to bridge any of a variety of processors to the peripherals that may connect to them. It helps reduce the number of buses in the system, and can make multi-processing systems more scalable. It is software-compatible with existing PCI applications.
Figure 1. HyperTransport Topology
Altera provides a robust 8-bit HyperTransport core that can be implemented on Stratix® series devices, including some transceiver variants. DDR links of up to 500 MHz are available for as much as 16-Gbps total throughput. Independently buffered virtual channels reduce the incidence of stalling, improving overall system efficiency. The IP Toolbench and MegaWizardTM Plug-Ins make customization of the core during system design easy, minimizing design time.
Stratix V GX FPGAs, Stratix IV GX FPGAs, HardCopy® V ASICs, and HardCopy IV GX ASICs include dedicated circuitry to allow support for HyperTransport 1.0 and 3.0 standards, at data rates up to 3.2 Gbps and bus widths up to 16 bits.
- Stratix V FPGAs
- Stratix IV FPGAs
- Stratix II FPGAs
- Stratix FPGAs
- Arria® V FPGAs
- HardCopy V ASICs
- HardCopy IV ASICs
- The Stratix II Characterization Report is available upon request; contact your local Altera® sales office