HyperTransport™ technology is a high-speed protocol for use in connecting peripherals to computers, mobile computers, servers, communication systems, network equipment, and embedded equipment. It provides up to 128-Gbps aggregate bandwidth, and can be configured with 2-, 4-, 8-, 16-, or 32-bit buses. It is intended to bridge any of a variety of processors to the peripherals that may connect to them. It helps reduce the number of buses in the system, and can make multi-processing systems more scalable. It is software-compatible with existing PCI applications.
Figure 1. HyperTransport Topology
Altera provides a robust 8-bit HyperTransport core that can be implemented on Stratix® and Stratix GX devices. DDR links of up to 500 MHz are available for as much as 16-Gbps total throughput. Independently buffered virtual channels reduce the incidence of stalling, improving overall system efficiency. The IP Toolbench and MegaWizard® Plug-Ins make customization of the core during system design easy and minimize design time.
Stratix IV GX FPGAs and HardCopy® IV GX ASICs include dedicated circuitry to allow support for HyperTransport 1.0 and 3.0 standards, at data rates up to 3.2 Gbps and bus widths up to 16 bits.
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Solutions
Devices
- Stratix IV (GX and E) FPGAs
- HardCopy IV (GX and E) ASICs
- Stratix II FPGAs
- Stratix FPGAs
- Stratix GX FPGAs
Characterization Report
- The Stratix II Characterization Report is available upon request; contact your local Altera® sales office
