PCI Express® (PCIe®) is a scalable, chip-to-chip interconnect standard protocol that services multiple end markets, such as computing and communications. Current PCI Express transmission speeds range from 2.5 GT/s (Gen1) to as high as 8 GT/s (Gen3), providing a large amount of bandwidth for various systems to support today’s ever-increasing network traffic requirements. Using the latest transceiver technology and a flexible protocol layer, Altera’ PCI Express intellectual property (IP) cores and device drivers provide the best performance and productivity for converging industries and emerging applications that require a common interconnect technology across a variety of FPGAs. The technical differentiation is achieved by combining the benefits of Altera’s FPGA silicon, PCI Express IP cores, and device drivers as a single, vertically integrated entity. The vertical integration of both the hardware and software layers provides maximum flexibility and performance for any system.
With the release of Altera’s next-generation Arria® 10 FPGAs and SoCs, the Altera Best-in-Class PCI Express IP portfolio accomplishes major development milestones: third-generation hardened PCI Express IP core, including the transaction layer and data link layer; second-generation hardened PHY IP core, including physical coding sublayer (PCS) and physical medium attachment (PMA); and first-generation complementary, enterprise-ready Linux and Windows device drivers.
Figure 1. PCI Express Block Diagram
Figure 2. A Typical PCI Express Application
Altera’s PCI Express IP core is available across many device families, which include a multitude of PCI Express IP core instances to provide the needed bandwidth for a variety of PCI Express applications. Table 1 provides an overview of the device support and the number of hardened PCIe IP core instances available for each device family.
Table 1. Device Support and Number of Hardened PCI Express IP Blocks
|Device Family||Number of Hardened PCI Express IP Blocks||PCI Express Performance|
|Arria 10||1 to 4 per device|
|Stratix® V||1 to 4 per device|
|Arria V||1 or 2 per device|
|Cyclone® V GT||2 per device|
|Cyclone V GX||1 or 2 per device|
|Stratix IV||2 to 4 per device|
|Cyclone IV GX||1 per device|
|Arria II GZ||1 per device|
|Arria II GX||1 per device|
PCI Express Compliance
Altera’s PCI Express IP cores and devices are complaint with the following PCI-SIG® specifications:
- PCI Express Base Specification, Rev 1.1 (2.5 GT/s)
- PCI Express Base Specification, Rev 2.0 (2.5 GT/s and 5.0 GT/s)
- PCI Express Specification, Rev 3.0 (2.5 GT/s, 5.0 GT/s, and 8.0 GT/s)
Information and Contact Details
For additional performance, productivity, and collateral information, please refer to the PCI Express Protocol or PCI Express Reference Designs and Application Notes web pages.
Altera's PCI Express IP is supported on the following device families:
- Arria 10 FPGAs and SoCs
- Stratix V FPGAs
- Arria V FPGAs
- Cyclone V FPGAs
- Stratix IV FPGAs
- Cyclone IV FPGAs
- Arria II FPGAs