PCI Express Hard IP

The PCI Express^® hard intellectual property (IP) block embeds the PCI Express protocol stack into the Altera^® FPGA. The hard IP block includes the transceiver modules, physical layer, data link layer, and transaction layer. In Stratix^® V GT, GX, and GS FPGAs, the hard IP block targets PCI Express Base Specification Rev. 3.0, 2.0, and 1.1. For Stratix IV (GX and GT) FPGAs and HardCopy^® IV GX ASICs, the hard IP block targets PCI Express Base Specification Rev. 2.0 and 1.1. The hard IP block in Arria^® V, Arria II, Cyclone V, and Cyclone^® IV GX FPGAs targets PCI Express Base Specification Rev. 1.1. Multiple copies of the PCI Express hard IP block are available in Stratix V and Stratix IV (GX and GT) FPGAs and HardCopy IV GX ASICs.

The PCI Express hard IP block is compliant with the following PCI-SIG^® specifications:

• PCI Express Base Specification, Rev 1.1 (2.5 Gbps)
• PCI Express Base Specification, Rev 2.0 (2.5 and 5.0 Gbps)
• PCI Express Base Specification, Rev 3.0 (2.5, 5.0, and 8.0 Gbps)

PCI Express Hard IP Benefits

• Resource savings of 8K to 30K logic elements (LEs) per hard IP instance, depending on the initial core configuration mode
• Embedded memory buffers included in the hard IP
• Pre-verified, protocol-compliant complex IP
• Shorter design and compile times with timing closed block
• Substantial power savings relative to a soft IP core with equivalent functionality

PCI Express Hard IP Block Description

Figure 1 shows a high-level block diagram of the PCI Express hard IP block.

Figure 1. PCI Express Hard IP Block

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Notes:

1. LMI: Local Management Interface
2. DPRIO: Dynamic Partial Reconfigurable Input/Output

Figure 2 shows the Stratix V GX FPGA PCI Express hard IP block.

Figure 2. Stratix V GX FPGA PCI Express Hard IP Block

The PCI Express hard IP block contains the following key features. Please refer to the PCI Express Compiler User Guide (PDF) to get the mapping of features to specific devices.

• PCI-SIG certified for PCI Express Base Specifications Rev 1.1 and 2.0. Stratix IV, Arria II, and Cylcone GX FPGAs are included on the integrators list 
• Dual mode to support both endpoint (legacy and native) and root port functionality
• Supports lane configurations of x1, x2, x4, and x8
• Configurable payload size up to 2,048 bytes (i.e., 128, 256, 512, 1,024, 2,048)
• Supports a maximum read request size up to 4,096 bytes
• Serial read/write access for reconfiguration of initial core parameters (DPRIO)
• Autonomous function support to enable the PCI-Express link to initialize before the FPGA is fully programmed (only in Stratix V, Arria V, and Cyclone V FPGAs)
• Configuration via Protocol (CvP) for programming the FPGA via the PCI Express interface (only in Stratix V, Arria V, and Cyclone V FPGAs)
• PIPE 2.0 and 3.0 PMA/PCS control
  • De-emphasis
  • Electrical idle
  • Modified compliance
  • Transmit margin
• Automatic lane reversal (transmit and receive)
• Power management
• One to four PCI Express hard IP blocks per device

Device	# of PCI Express Hard IP Blocks	PCI Express Performance
		Gen1 (2.5 Gbps)	Gen2 (5.0 Gbps)	Gen3 (8.0 Gbps)
Stratix V	1 to 4 per device
Stratix IV GT	2 to 4 per device
Stratix IV GX	2 to 4 per device
Arria V GX	1 or 2 per device
Arria V GT	1 or 2 per device
Arria II GZ	1 per device
Arria II GX	1 per device
Cyclone V GX	1 or 2 per device
Cyclone V GT	2 per device
Cyclone IV GX	1 per device
HardCopy IV GX	Up to 2 per device

For more information, refer to the PCI Express Compiler User Guide (PDF).

Related Links

Devices

• Stratix V FPGAs
• Arria V FPGAs 
• Arria II FPGAs
• Stratix IV GX FPGAs
• HardCopy IV GX ASICs
• Cyclone V FPGAs
• Cyclone IV GX FPGAs

PCI Express Protocol Standards

• PCI-SIG
• PCI Express Technical Library (membership is required to access most documents)
• PCI-SIG PCI Express Integrators List