PCI Express Hard IP

The PCI Express hard intellectual property (IP) block embeds all layers of the PCI Express protocol stack. It includes the transceiver modules, physical layer, data link layer, and transaction layer. The hard IP block in Stratix^® IV GX FPGAs and HardCopy^® IV GX ASICs targets PCI Express Base specification 1.1 and 2.0, while the hard IP block in Arria^® II GX and Cyclone^® IV GX FPGAs targets PCI Express Base specification 1.1. Multiple copies of the PCI Express hard IP block are available in Stratix IV GX FPGAs and HardCopy IV GX ASICs.

The PCI Express hard IP block is compliant with the following PCI-SIG specifications:

• PCI-Express Base Specifications, Rev 1.1 (2.5 Gbps)
• PCI-Express Base Specifications, Rev 2.0 (2.5 and 5.0 Gbps)

PCI Express Hard IP Benefits

• Resource savings of 8K to 30K logic elements (LEs) per hard IP instance, depending on the initial core configuration mode
• Embedded memory buffers included in the hard IP
• Pre-verified, protocol-compliant complex IP
• Shorter design and compile times with timing closed block
• Substantial power savings relative to a soft IP core with equivalent functionality

PCI Express Hard IP Block Description

Figure 1 shows a high-level block diagram of the PCI Express hard IP block.

Figure 1. PCI Express Hard IP Block

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Notes:

1. LMI: Local Management Interface
2. DPRIO: Dynamic Partial Reconfigurable Input/Output

The PCI Express hard IP block contains the following key features. Please refer to the PCI Express Compiler User Guide (PDF) to get the mapping of features to specific devices.

• Dual mode to support both endpoint (legacy and native) and root port functionality
• Support for initial lane configurations of x1, x2, x4, and x8
  • Link width down configuration to intermediate widths
  • Receive and transmit Avalon^® Streaming (ST) user interface to and from the hard IP block's transaction layer
• Selection between one or two virtual channel interfaces
• Debug and status access for real-time system monitoring
• User datapath width of 128 bits (x8, x4) and 64 bits (x8, x4, x2, x1)
• High-performance transaction layer interface
  • Two virtual channels
  • Single function
  • Vendor-defined message pass-through
  • High-performance bandwidth, close to the maximum theoretical bandwidth
• Advance error reporting
  • ECRC generation, checking, and handling or passing to and from the application layer
  • Surprise down error reporting and handling
  • Receiver overflow error reporting and handling
  • Complete abort error reporting and handling
  • Flow control protocol error reporting and handling
• Configurable up to six base address registers (BARs) plus expansion ROM
  • Support 32-bit and 64-bit addressing
• Support for all memory, I/O, configuration, and message transactions
• 64 outstanding request message tags
• Configurable maximum payload size up to 2,048 bytes (i.e., 128, 256, 512, 1,024, 2,048)
• Supports a maximum read request size up to 4,096 bytes
• Retry buffer size of 16 Kbytes
• Configurable receive buffer size of 16 Kbytes per virtual channel
  • Dedicated DPRAM interface with configurable segment size
  • Bypass and store-and-forward on receive buffers
  • Static configuration of one or two virtual channels using separate interfaces
  • Virtual channel arbitration of strict (high/low) and round robin
• Configuration space registers
  • Included with the transaction layer
• Serial read/write access for reconfiguration of initial core parameters (DPRIO)
• Non-intrusive local management interface access to configuration space in endpoint mode
  • Avalon Memory-Mapped (MM) 32-bit parallel bus
• Synchronous status and debug interface
  • Critical test signals used for system debugging
  • Status reporting of errors and events
• PCI Express to PLD fabric hard adapter to retime and widen datapath (when necessary) to and from the user application
• PIPE 2.0 PMA/PCS control
  • De-emphasis
  • Electrical idle
  • Modified compliance
  • Transmit margin
  • Lane-to-lane de-skew tolerance of 80 UI
• Automatic lane reversal (transmit and receive)
• Physical layer packet checking (receiver error)
  • 8B/10B decode error
  • Disparity error
  • Elastic buffer overflow/underflow
  • Lane de-skew error
  • Framing error
• Power management
  • All power states (emulate D1, D2, and L2)
  • Software-initiated link power management (PME and wakeup)
  • Legacy PCI power management support (D0, D3HOT, and D3COLD)
  • Native active state power management L0s and L1 state support
  • PCI Express hard IP is powered down when it is not used
• One INTx emulation for an endpoint and four INTx emulation for a root port
• Configurable up to 32 message-signaled interrupts and 2048 MSI-X
• Completion timeout control and capabilities registers
• One to four PCI Express hard IP block instances
• The transceiver blocks are not dedicated to the PCI Express hard IP block
  • PCI Express hard IP block with initial link configuration of x1, x2, or x4 can share transceiver blocks with other user applications that require transceiver channels

For more information, refer to the PCI Express Compiler User Guide (PDF).

Related Links

Devices

• Arria II GX FPGAs
• Stratix IV GX FPGAs
• HardCopy IV GX ASICs
• Cyclone IV GX FPGAs

PCI Express Protocol Standards

• PCI-SIG
• PCI Express Technical Library (membership is required to access most documents)
• PCI-SIG PCI Express Integrators List