- Altera RapidIO Intellectual Property (IP) Core
- RapidIO Development Environment (PCI Express Development Kit, Stratix II GX Edition)
- Stratix IV FPGAs
- HardCopy IV ASICs
- Stratix II GX FPGAs
- Arria GX FPGAs
- Arria II GX FPGAs
- Cyclone IV GX FPGAs
Integrated Serial RapidIO Solutions
Altera provides a range of complete FPGA solutions for the development of custom Serial RapidIO® processing elements, bridges, and switches. Device and IP support is available for x1, x4, and 8-bit parallel. The solutions, which include configurable Serial RapidIO IP cores and development boards, allow you to concentrate on the core functions of the system design by providing:
- Simple and fast protocol implementation
- Reduced design risks
- Shortened development times
The following Altera® devices feature a fully integrated Serial RapidIO solution:
- Stratix® IV GX FPGAs
- HardCopy® IV GX ASICs
- Stratix II GX FPGAs
- Arria® II GX FPGAs
- Arria GX FPGAs
- Cyclone® IV GX FPGAs
Embedded transceivers support the physical layers of the protocol, while the transport and logical layers are supported in IP, allowing the protocol to be implemented in a single device. Table 1 gives an overview of the complete Serial RapidIO solution for Altera devices.
| Table 1. Complete Serial RapidIO Solution | |
| Solution | Description |
|---|---|
| Device |
|
| Physical Interface | Integrated transceiver provides physical layer of the serial protocol support provided for x1 and x4 at 1.25 Gbps, 2.5 Gbps, and 3.125 Gbps |
| Altera RapidIO IP Cores | RapidIO MegaCore® Functions |
| Partner RapidIO Core | Partner RapidIO IP Cores |
| Development Boards | |
| Characterization Report | Contact your local Altera sales representative |
External Transceiver-Based Serial RapidIO Solutions
For high-volume, cost-sensitive applications, use Cyclone IV, Cyclone III, and Cyclone II FPGAs with an external transceiver (or PHY device). For applications requiring the highest density and performance use:
- Stratix IV E FPGAs
- HardCopy IV E ASICs
- Stratix III FPGAs
- HardCopy III ASICs
- Stratix II FPGAs
- HardCopy II ASICs
Table 2 shows Altera FPGAs with external PHY solutions for the Serial RapidIO standard.
| Table 2. External PHY Solutions for Serial RapidIO Standard | |
| Solution | Description |
|---|---|
| Devices | |
| Altera RapidIO IP Cores | RapidIO MegaCore Functions |
| Partner Boards | Stratix II FPGA and PMC 8358 SERDES Universal Baseband Processing Module |
| Partner RapidIO IP Core | Partner RapidIO IP Cores |
Technology Background
Serial RapidIO is a high-performance, point-to-point, packet-switched interconnect technology defined by the RapidIO Trade Association. Serial RapidIO transmits data and control information between microprocessors, digital signal processing (DSP) functions, communication or network processors, and I/O devices in embedded systems. Figure 1 illustrates a typical subsystem in a wireless application.
Figure 1. Serial RapidIO Topology in a Wireless Subsystem
Full-duplex point-to-point links are established with single or multiple high-speed serial lanes (1x and 4x are currently defined), and industry-standard 8B/10B-encoded data transmission at signaling rates of 1.25, 2.50, or 3.125 Gbaud for peak bandwidth of up to 20 Gbps. The initial RapidIO specifications were based on source-synchronous clocking (or bit-parallel clock and data), but subsequent specifications have adopted serialized clock and data transmission to reduce pin requirements and extend signal reach, making the Serial RapidIO standard well-suited for chip-to-chip, board-to-board, and backplane interconnects.
Related Links
Devices
- Stratix IV FPGAs
- HardCopy IV ASICs
- Stratix II GX FPGAs
- Arria GX FPGAs
- Arria II GX FPGAs
- Stratix III FPGAs
- HardCopy III ASICs
- Stratix II FPGAs
- HardCopy II ASICs
- Cyclone IV FPGAs
- Cyclone III FPGAs
- Cyclone II FPGAs
Protocol Standard
- RapidIO Trade Association. The Tsi620 contains all the benefits of Tundra's family of RapidIO switches. In addition, the device interfaces to low-cost FPGAs through a Stratix III FPGA port that transmits the RapidIO logical and transport layer over an XGMII physical interface for connection to non-serializer/deserializer (SERDES) FPGAs.
