Integrated RapidIO Solutions
Altera provides a range of complete FPGA solutions for the development of custom RapidIO® processing elements, bridges, and switches. Device and intellectual property (IP) support are available for 1x, 2x, and 4x serial link widths. RapidIO II MegaCore® function complies with the RapidIO Specification Revision 2.2.
RapidIO Specification Revision 2.2 supports higher performance physical layer for 5.0 and 6.25 Gbaud rates with IDLE2 sequence long control symbol that is compatible with decision feedback equalization (DFE) that can be applied in RapidIO links implemented across lossy backplanes.
RapidIO II MegaCore function complies with the RapidIO Specification Revision 2.2
- 1x / 2x / 4x serial with integrated transceivers
- IDLE2 sequence - long control symbol
- All five standard serial data rates supported:
- 6.25, 5.0, 3.125, 2.5, and 1.25 Gbaud using IDLE2 sequence or long control symbol
- Available on Stratix® V and Arria® V devices
RapidIO MegaCore function complies with RapidIO Specification Revisions 1.3 / 2.1
- 1x / 2x / 4x serial with integrated transceivers
- IDLE1 sequence - short control symbol
- All four standard serial data rates supported:
- 5.0, 3.125, 2.5, and 1.25 Gbaud
RIOLAB certified RapidIO Revision 1.3 MegaCore function
The solutions, which include configurable RapidIO IP cores and development boards, allow you to concentrate on the core functions of the system design by providing:
- Simple and fast protocol implementation using Qsys - Altera's System Integration Tool
- Reduced design risks
- Shortened development times
Embedded transceivers support the physical layers of the protocol, while the transport and logical layers are supported in IP, allowing the protocol to be implemented in a single device.
Figure 1: Altera RapidIO II or RapidIO MegaCore Function Block Diagram
In addition to fully compliant Logical Modules (e.g. Input / Output, Doorbell), Altera also provides direct Transport Layer access for user-designed modules, such as Message Passing, Data Streaming or any other application specific modules.
Table 1 gives an overview of the complete RapidIO solutions for Altera® devices.
| Solution | Description |
|---|---|
| Device | |
| Altera RapidIO IP cores | |
| Development boards | Altera 28 nm Development Kits Portfolio |
| Characterization report | Contact your local Altera sales representative |
(*) For device support details, such as lane rates, link widths, and speed grades, refer to the RapidIO MegaCore function user guides.
RapidIO is a high-performance, point-to-point, packet-switched interconnect technology defined by the RapidIO Trade Association. RapidIO transmits data and control information between microprocessors, digital signal processing (DSP) functions, communication or network processors, and I/O devices in embedded systems. Figure 1 illustrates a typical subsystem in a wireless application.
Figure 2. RapidIO Topology in a Wireless Subsystem
Full-duplex point-to-point links are established with single or multiple high-speed serial lanes (1x, 2x, and 4x are currently implemented), and industry-standard 8B/10B-encoded data transmission at signaling rates of up to 6.25 Gbaud for peak bandwidth of up to 25 Gbaud. The RapidIO standards are well-suited for chip-to-chip, board-to-board, and backplane interconnects.
