Integrated Serial RapidIO Solutions
Altera provides a range of complete FPGA solutions for the development of custom Serial RapidIO® processing elements, bridges, and switches. Device and intellectual property (IP) support are available for x1, x4, and x8 parallel interfaces. The solutions, which include configurable Serial RapidIO IP cores and development boards, allow you to concentrate on the core functions of the system design by providing:
- Simple and fast protocol implementation
- Reduced design risks
- Shortened development times
Embedded transceivers support the physical layers of the protocol, while the transport and logical layers are supported in IP, allowing the protocol to be implemented in a single device. Table 1 gives an overview of the complete Serial RapidIO solution for Altera® devices.
| Table 1. Complete Serial RapidIO Solution | |
| Solution | Description |
|---|---|
| Device | |
| Physical interface | Integrated transceivers provide physical layer of the serial protocol support provided for x1 and x4 at 1.25 Gbps, 2.5 Gbps, 3.125 Gbps, and 5 Gbps |
| Altera RapidIO IP cores | RapidIO MegaCore® functions |
| Development boards | |
| Characterization report | Contact your local Altera sales representative |
External Transceiver-Based Serial RapidIO Solutions
For high-volume, cost-sensitive applications, use Cyclone IV, Cyclone III, and Cyclone II FPGAs with an external transceiver (or PHY device). For applications requiring the highest density and performance, use:
- Stratix V E FPGAs
- Stratix IV E FPGAs
- Stratix III FPGAs
- Stratix II FPGAs
- HardCopy V ASICs
- HardCopy IV E ASICs
- HardCopy III ASICs
- HardCopy II ASICs
Table 2 shows Altera FPGAs with external PHY solutions for the Serial RapidIO standard.
| Table 2. External PHY Solutions for Serial RapidIO Standard | |
| Solution | Description |
|---|---|
| Devices | |
| Altera RapidIO IP cores | RapidIO MegaCore functions |
| Partner boards | Stratix II FPGA and PMC 8358 SERDES Universal Baseband Processing Module |
Technology Background
Serial RapidIO is a high-performance, point-to-point, packet-switched interconnect technology defined by the RapidIO Trade Association. Serial RapidIO transmits data and control information between microprocessors, digital signal processing (DSP) functions, communication or network processors, and I/O devices in embedded systems. Figure 1 illustrates a typical subsystem in a wireless application.
Figure 1. Serial RapidIO Topology in a Wireless Subsystem
Full-duplex point-to-point links are established with single or multiple high-speed serial lanes (x1 and x4 are currently defined), and industry-standard 8B/10B-encoded data transmission at signaling rates of 1.25, 2.50, 3.125, or 5 Gbaud for peak bandwidth of up to 20 Gbps. The initial RapidIO specifications were based on source-synchronous clocking (or bit-parallel clock and data), but subsequent specifications have adopted serialized clock and data transmission to reduce pin requirements and extend signal reach, making the Serial RapidIO standard well-suited for chip-to-chip, board-to-board, and backplane interconnects.
Related Links
Devices
- Stratix V FPGAs
- Stratix IV FPGAs
- Stratix III FPGAs
- Stratix II GX FPGAs
- Stratix II FPGAs
- HardCopy IV ASICs
- HardCopy III ASICs
- HardCopy II ASICs
- Arria V FPGAs
- Arria II FPGAs
- Arria GX FPGAs
- Cyclone V FGPAs
- Cyclone IV FPGAs
- Cyclone III FPGAs
- Cyclone II FPGAs
