Serial ATA (SATA) and Serial Attached SCSI (SAS) are data storage protocol standards that have the primary function of transferring data (directly or otherwise) between the host system and mass storage devices (e.g., hard disk drives, optical drives, and solid-state disks). These serial storage protocols offer several advantages over older parallel storage protocol (ATA and SCSI) interfaces:
- Faster data transfer
- Ability to remove or add devices while operating (hot swapping)
- Hot swapping can only occur when it is supported by the operating system
- Thinner cables for more efficient air cooling
- Increased operation reliability
Altera SATA and SAS
Altera developed SATA and SAS solutions based on the latest FPGAs and ASICs with transceivers. Stratix® V GX, Stratix IV GX, Arria® V, Arria II GX, Arria II GZ, Cyclone® V and Cyclone IV GX FPGAs and HardCopy® IV GX ASICs support the electrical and signal requirements for SATA and SAS (see Table 1). Altera® FPGAs and HardCopy ASICs, coupled with SATA and SAS intellectual property (IP), offer a solution for developing storage interfaces on a single chip.
|Table 1. Altera FPGA and HardCopy ASIC SATA and SAS Support|
|Arria II GX||-|
|Cyclone IV GX||
|HardCopy IV GX||-|
SATA and SAS IP
The IP portion of the Altera solution is instrumental to the SATA and SAS I/O connectivity. The FPGA and ASIC provide the foundation, but the IP makes the SATA and SAS I/O possible. Altera's partners developed SATA and SAS IP for both host and device interfaces. As shown in Figure 1, the IP core has all the basic components of a SATA and SAS interface: a physical layer interface that connects to the embedded transceivers in the Altera devices, a link layer, and a transport layer.
The Altera SATA and SAS solutions are ideal for high-throughput storage applications. Using the IP cores, along with Altera FPGAs and HardCopy ASICs, provides a powerful foundation to build storage solutions that connect to host systems to storage. You can use the device and host cores independently (as seen in Figure 2) or together (used as a bridge).
Figure 2. Using IP Cores with Altera FPGAs and HardCopy ASICs