Altera's Stratix II GX FPGA Complete SerialLite II Solution
Altera® SeriaLite II is a complete protocol solution based on the Stratix® II GX device, the configurable SerialLite II intellectual property (IP) core, development board, and collateral. The solution enables easy, high-speed serial protocol implementation, which reduces design risk, shortens development times and allows you to concentrate on the core functions of your system design.
SerialLite II is Altera’s second-generation lightweight serial interconnect protocol for a wide array of chip-to-chip, board-to-board, and backplane applications. SerialLite II builds on the success of SerialLite, extending the performance range from 622 Mbps to 102 Gbps in Stratix II GX FPGAs, and reducing the logic requirements by an average of 60 percent, to deliver the lowest-cost serial interconnect solution.
Table 1 provides an overview of the Stratix II GX device complete SerialLite II interconnect solution
Technology Background
The SerialLite II protocol, like its predecessor, is defined as a lightweight point-to-point serial interconnect with low protocol overhead, minimal data transfer latency, and a range of optional features to minimize logic requirements for the most cost-effective implementations.
SerialLite defined a full-duplex protocol based on a 16-bit data path width (per lane), which resulted in minimal logic consumption for applications requiring symmetrical (transmit and receive) lane widths with lane rates from 1.6 to 3.125 Gbps.
SerialLite II builds on the success of SerialLite with optimized support for simplex, asymmetric, and broadcast data flows, and extended scalability with optional data path widths (8-, 16-, or 32-bit per lane) for optimal implementations of lane rates below 1.5 Gbps and up to 6.375 Gbps.
Table 2 summarizes the key features and benefits of the SerialLite II protocol.
| Table 2. Features and Benefits of SerialLite II |
| Feature |
Options |
Benefits |
| Data Flow |
Full-duplex, Simplex, Asymmetric, or Broadcast |
Reduced logic for simplex, asymmetric, or broadcast applications |
| Data Type |
Packet or Streaming |
Support for a variety of applications |
| Link Width |
1 to 16 Lanes |
Scalable link throughput from 622 Mbps to 102 Gbps in each direction |
| Lane Rate |
622 Mbps to 6.375 Gbps |
| Datapath Width |
8-, 16-, or 32-bit (per lane) |
Reduced logic for lane rates below 1.5 Gbps and scalability to 6.375-Gbps lane rates |
| Encoding |
8B/10B |
Industry-standard encoding for the most reliable clock and data recovery |
| Scrambling |
Payload and Idle, or None |
Reduced EMI for high lane rates |
| Reference Clock |
Asynchronous or synchronous |
Suitable for chip-to-chip, board-to-board, and backplane applications |
| Polarity Reversal |
Yes or No |
Implement the functionality required for your specific application for a cost-optimized solution |
| Data Integrity Protection |
CRC-32, CRC-16, or None |
| Packet Type |
Data, Priority, or Both |
Optional logic to insert high-priority data or control information |
| Flow Control |
Data Packet, Priority Packet, Both, or None |
Implement the functionality required for your specific application for a cost-optimized solution |
| Retry-on-Error |
Priority Packet or None |
Increased link reliability |
| Channel Multiplexing |
Yes or No |
Support for applications with multiple logical channels |
| Atlantic™ Interface |
Data and Priority Ports |
Well-defined interface to user logic, and a variety of Altera MegaCore® functions to accelerate design cycles for unique bridging solutions |
Hardware Testing
To ensure the highest reliability, Altera’s SerialLite II solutions are extensively tested in hardware. The SerialLite II MegaCore Function (v.1.0.0) has been tested on dual Stratix GX development boards in a range of configurations, including all of the data flow options, packet and streaming data, a variety of link widths, lane rates up to 3.125 Gbps. The tests were conducted both with and without optional features enabled, such as data integrity protection, data and priority packets, flow control, and retry-on-error.
Related Links
SerialLite II
SerialLite
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