The SERDES Framer Interface Level 5 (SFI-5) is a chip-to-chip and chip-to-module protocol that targets 40-Gbps applications. The standard is intended to support up to 50 Gbps of throughput to account for 25 percent overhead, due to forward error correction (FEC) code, and could also be combined into multiple instances to achieve 100 Gbps of aggregate bandwidth.
The interface can be used for a connection between an optical transport node (OTN ) or SONET/SDH Framer and a forward error correction (FEC) device; an OTN or SONET/SDH Framer and an external SERDES; or from a FEC device and an external SERDES; or from a FED device and an optical transponder. Figures 1 and 2 show typical examples of SFI-5 applications.
Figure 1. 40-Gbps SFI-5 Transponder/Regenerator Cards
Notes:
- OC-768 = optical carrier with line rate 39,813.12 Mbps
- OTN Rx = optical transport node receiver
- FEC = forward error correction
- EFEC = enhanced forward error correction
- O/H = overhead
Figure 2. 40-Gbps SFI-5 Mux Application
Altera’s Stratix® IV GT, Stratix IV GX, and Stratix II GX FPGAs and HardCopy® IV ASICs support the SFI-5 interface in 40-Gbps Framer, FEC, and bridging applications. The Stratix II GX family includes devices that have been hardware tested to verify support of SFI-5, and embed up to 20 high-speed serial transceiver channels that can operate at the 2.488-Gbps to 3.125-Gbps rate necessary for SFI-5.1. Stratix IV GX FPGAs are available with up to 48 transceiver channels that can operate in the 2.488-Gbps to 3.125-Gbps range. Stratix IV GT FPGAs are available with up to 24 transceiver channels that can operate in the 9.95 to 11.3 Gbps range for SFI-5.2 operation.
Contact your local Altera® sales representative for more information on SFI-5 or 40-Gbps Framer and FEC solutions.
