Serial Gigabit Media Independent Interface
Altera’s Stratix® III devices allow you to easily implement Serial Gigabit Media Independent Interface (SGMII) connectivity with its LVDS I/Os. Stratix III FPGAs have built-in serializer/deserializer (SERDES) circuitry that supports high-speed LVDS interfaces at data rates of up to 1.25 Gbps. The SERDES circuitry is configured to support source synchronous and asynchronous serial data communication for SGMII interfaces.
SGMII Applications
A typical chip-to-chip SGMII system might use between 16 and 48 full-duplex SGMII links. Stratix III FPGAs allow the implementation of multiple full-duplex channels because they offer up to 132 LVDS transmitters and receivers in the largest devices. For applications with a high number of SGMII links, the Stratix III LVDS I/Os offer a preferred solution with low-power differential signaling capability.
Figure 1. SGMII Connectivity with a Stratix III FPGA and PHY Device
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Note:
- Examples of PHY Device are Marvell 88E1112S, 88E1240 and Broadcom BCM5461S, 8012S.
Stratix III FPGAs can also provide connectivity between a Gigabit Ethernet small form-factor pluggable (SFP) optical or copper module port, a host processor, and a backplane driver on a line card. Stratix III devices also support a wide range of interfaces with other devices on a typical line card.
Figure 2. SGMII Connectivity with a Stratix III FPGA and SFP Module
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Stratix III SGMII Features
The Stratix III FPGA family supports three receiver data path modes: DPA (dynamic phase alignment) mode, non-DPA mode, and soft-CDR mode. For SGMII interfaces, data communication can be achieved using soft-CDR mode and DPA mode (source synchronous mode) in the receive data path.
Soft-CDR mode in Asynchronous Systems—In these systems there is no source synchronous clock sent with the data channels from the upstream transmitter. The transmitter and receiver use reference clocks from two different sources
Soft-CDR mode in Synchronous Systems—The transmitter and receiver use reference clocks from the same sources
Source synchronous mode—In these systems a source synchronous clock is sent with the data channels. The receiver nodes use this source synchronous clock to recover the received data
The Stratix III LVDS transmitters have programmable output voltage settings, output common mode range, and settings for pre-emphasis. On the receive side, the Stratix III FPGAs can operate with a wide range of input voltage amplitudes and input common modes.
Triple-Speed Ethernet MegaCore
Altera offers a complete innovative custom logic solution for Ethernet applications with Stratix III FPGAs using the Triple-Speed Ethernet (TSE) MegaCore® function for physical media attachment, physical coding sublayer, and media access control. The TSE MegaCore function uses the LVDS hard macro of the Stratix III FPGA configured as soft-CDR. Contact your Altera sales team for more information on the TSE MegaCore.
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