The LVDS I/Os in Altera’s Stratix® IV and Stratix III FPGAs and HardCopy® IV and HardCopy III ASICs allow you to easily implement the Serial Gigabit Media Independent Interface (SGMII) for 10/100/1000 Mb or Gigabit Ethernet. These devices have built-in serializer/deserializer (SERDES) circuitry that supports high-speed LVDS interfaces at data rates up to 1.25 Gbps. The SERDES circuitry is configured to support source synchronous and asynchronous serial data communication for the SGMII interface. This SGMII solution meets the SGMII specification and saves cost and power in systems that have low to high port-count Gigabit Ethernet per device.
The integrated gigabit serial transceivers in Stratix IV GX, Stratix II GX, Arria® series, and HardCopy IV GX devices also support the SGMII interface for 10/100/1000 Mb and Gigabit Ethernet.
SGMII applications
A typical chip-to-chip SGMII application may use between 12 and 48 full-duplex SGMII for 10/100/1000-Mb Ethernet or Gigabit Ethernet links. For applications with a low to high number of SGMII links, the LVDS I/Os in Stratix IV and Stratix III FPGAs and HardCopy IV and HardCopy III ASICs offer a preferred solution with low-power differential signaling capability, because these devices offer up to 132 LVDS transmitter and receiver pairs in the largest devices.
Figure 1 shows examples of a Gigabit Ethernet line card design consisting of the Altera Triple Speed Ethernet MegaCore function connected by the SGMII interface either directly to a backplane or through a PHY device to a 10/100/1000-Mbps Ethernet network or backplane. These two examples show that both LVDS I/O and serial transceivers in different Altera® devices can be used to realize the SGMII interface.
Figure 1. SGMII Connectivity Choices with an Altera Device and a PHY Device
Note:
- Marvell 88E1112S and 88E1240 and Broadcom BCM5461S and 8012S are examples of PHY devices.
Stratix IV, Stratix III, HardCopy IV, and HardCopy III devices can also provide connectivity between a Gigabit Ethernet small form-factor pluggable (SFP) optical or copper module port, a host processor, and a backplane driver on a line card using SGMII interface with LVDS I/O. These devices also support a wide range of interfaces with other devices on a typical line card. Figure 2 shows two examples of a Gigabit Ethernet line card with an Altera device connected by the SGMII interface to a 10/100/1000 Mbps or Gigabit Ethernet SFP pluggable module with LVDS I/O and serial transceiver, respectively.
Figure 2. SGMII Connectivity Choices with an Altera Device and an SFP Module
SGMII features in Altera devices
Stratix IV, Stratix III, HardCopy IV, and HardCopy III devices support three receiver datapath modes with LVDS I/Os:
- Dynamic phase alignment (DPA) mode
- Non-DPA mode
- Soft-clock data recovery (CDR) mode
For SGMII interfaces, use soft-CDR mode and DPA mode (source synchronous mode) in the receive datapath for data communication.
- Soft-CDR mode in asynchronous systems. In these systems, there is no source synchronous clock sent with the data channels from the upstream transmitter. The transmitter and receiver use reference clocks from two different sources.
- Soft-CDR mode in synchronous systems. The transmitter and receiver use reference clocks from the same sources.
- Source synchronous mode. In these systems, a source synchronous clock is sent with the data channels. The receiver nodes use this source synchronous clock to recover the received data.
The LVDS transmitters in Stratix IV, Stratix III, HardCopy IV, and HardCopy III devices have programmable output voltage settings, output common mode range, and settings for pre-emphasis. On the receive side, these devices can operate with a wide range of input voltage amplitudes and input common modes.
Triple Speed Ethernet MegaCore function
Altera offers a complete innovative custom logic solution for Ethernet applications with Stratix IV, Stratix III, HardCopy IV, and HardCopy III devices using the Triple Speed Ethernet MegaCore® function for physical media attachment, physical coding sublayer, and media access control. The Triple Speed Ethernet MegaCore function uses the LVDS hard macro of the Stratix IV, Stratix III, HardCopy IV, or HardCopy III device configured as soft-CDR. Contact your Altera sales representative for more information about the Triple Speed Ethernet MegaCore function.
Related links
- Stratix IV FPGAs
- Stratix III FPGAs
- Stratix II GX FPGAs
- Arria FPGAs
- HardCopy IV ASICs
- HardCopy III ASICs
- Stratix III Device Handbook: High-Speed Differential I/O Interfaces and DPA chapter (PDF)
- Small Form-factor Pluggable (SFP) Transceiver MultiSource Agreement (MSA) (PDF)
- AN 518: SGMII Interface Implementation Using Soft-CDR Mode of Stratix III Devices (PDF)
