Altera SDH/SONET Protocol Solutions

Altera provides a range of solutions for synchronous digital hierarchy (SDH) and SONET protocols. The solutions enable simple and fast protocol implementation, reducing design risk, shortening development times, and allowing you to concentrate on the core functions of your system design.

By utilizing built-in transceivers to implement SDH/SONET and other protocols, Stratix^® IV GX FPGAs, Arria^® II GX FPGAs, HardCopy^® IV GX ASICs, and Stratix II GX FPGAs provide a fully integrated SDH/SONET solution for multi-rate applications including chip-to-chip, backplane, and line-side interfacing. Table 1 provides an overview of the complete SDH/SONET solution.

External transceiver solutions

Use high-density Stratix IV E, HardCopy IV E, Stratix III, HardCopy III, Stratix II, or HardCopy II devices with an external transceiver (or PHY device) in applications requiring the highest density and performance.

Technology background

SONET/SDH-based protocols are commonly used for backplane connectivity in networking systems. They allow you to reuse pre-defined standards of the SONET/SDH specifications such as framing, scrambling, and error detection. This helps reduce the overall system definition and design complexity. SONET/SDH backplanes tend to be deployed in two styles: distributed switch fabric (see Figure 1) and centralized switch fabric (see Figure 2). Centralized switch fabric relies on dedicated switch cards, while distributed switch fabric implements the switching functionality on the line card. Altera provides solutions for both implementations. Figures 1 and 2 show the difference between the two types of switch fabric.

Figure 1. Distributed Switch Fabric

Figure 2. Centralized Switch Fabric

Altera provides a complete solution for implementing SONET/SDH over a backplane. Stratix IV GX, Arria II GX, HardCopy IV GX, Stratix II GX, and Stratix GX devices offer transceivers capable of supporting data rates up to OC-48 (2.5 Gbps) using a single channel. Dedicated features—such as A1A2 pattern detectors and word aligners—are implemented within the transceiver core to reduce the amount of FPGA fabric required to support the protocol. The flexible phase-locked loop (PLL) structure ensures that all data rates can be achieved from a single clock source.

Related links

Devices

• Stratix IV FPGAs
• Arria II GX FPGAs
• HardCopy IV ASICs
• Stratix II GX FPGAs
• Stratix GX FPGAs
• Stratix III FPGAs
• HardCopy III ASICs
• Stratix II FPGAs
• HardCopy II ASICs
• Cyclone^® III FPGAs
• Cyclone II FPGAs

Protocol standard

• Optical Internetworking Forum (OIF) Information