SPI-4.2: System Packet Interface Level 4, Phase 2

The system packet interface level 4, phase 2 (SPI-4.2) protocol (alternatively known as POS-PHY Level 4 or PL4) has gained broad industry acceptance as the standard interface for 10 Gbps and higher data rate packet and cell transfers between PHY and link layer devices in multi-gigabit applications. The system applications include packet over SONET/SDH (STS-192/STM-64), 10-Gigabit Ethernet, and multichannel Gigabit Ethernet. Figure 1 shows the SPI-4.2 topology.

Figure 1. SPI-4.2 Topology

Notes:

1. CDR = clock data recovery
2. SERDES = serializer/deserializer
3. POS = packet over SONET

The Altera^® POS-PHY Level 4 (PL4) MegaCore^® function was developed based on the Optical Internetworking Forum (OIF) SPI-4.2 specification and has been tested successfully in Stratix^® GX FPGAs with SPI-4.2 devices from various vendors. Altera's PL4 solution provides the greatest flexibility available. Single- or multiport configurations are supported, with a variety of FIFO sizes and structures that allow shared or independent buffers. A number of data bus widths are also supported. Multiple burst sizes, the availability of an “almost-empty” FIFO flag, and support for continuous burst mode all enable great optimization for a given application. The Atlantic^TM interface allows easy interconnect to other intellectual property (IP) modules without glue logic, and the IP Toolbench and MegaWizard^TM Plug-Ins make customization of the core during system design easy and minimize the design time, minimizing design time.

Supporting SPI-4.2 performance as high as 1.25 Gbps per LVDS data link (20 Gbps total throughput rate) ensures that mainstream data rate applications can be accomplished with comfortable margins and in less expensive lower-speed-grade devices. Moreover, it ensures that leading-edge designs can be realized with currently available technology. At these speeds, the challenge of managing skew becomes significant. Stratix and Arria FPGA series, with an integrated deskewing circuitry known as dynamic phase alignment (DPA), easily support data transfer rates as high as 1.25 Gbps. This integrated function is also included in all Stratix and Arria^® FPGA series devices (up to 1,000 Mbps per LVDS data link) and all HardCopy^® ASICs (except in HardCopy Stratix and HardCopy APEX ASICs). Altera's Cyclone^® FPGA series devices support SPI-4.2 without DPA up to 622 Mbps per LVDS I/O channel.

Related links

Cores

• POS-PHY Level 4 MegaCore Function 

Devices

• Stratix FPGA series
• Arria FPGA series
• HardCopy ASICs
• Cyclone FPGA series

Characterization report

• The SPI-4.2 Characterization Report is available upon request; contact your local Altera sales office

Protocol standard

• SPI-4.2 Protocol Specification (PDF)
• Optical Internetworking Forum (OIF) Information