Many applications require proprietary functionality not offered by mainstream protocols. For these applications, Altera® transceivers offer 'basic' mode. Basic mode allows access to the building blocks within the transceiver. These can be individually configured or bypassed to meet your proprietary transceiver requirements.
Table 1 lists the basic modes available in Altera's transceiver devices and provides a list of the transceiver physical coding sublayer (PCS) blocks available in this mode.
| Table 1. Basic Modes and PCS Blocks | ||||||
| Transceiver Feature | Arria® II GX FPGAs | Stratix® GX FPGAs (Basic Mode) |
Stratix IV GT FPGAs | Stratix IV GX, Stratix II GX FPGAs, and HardCopy® IV GX ASICs |
Cyclone® IV GX FPGAs | |
|---|---|---|---|---|---|---|
| Basic Single Width | Basic Double Width |
|||||
| Data Rates (Gbps) | 0.155 to 3.75 | 0.500 to 3.1875 | 2.5 to 11.3 | 0.600 to 6.5 | Stratix IV GX: 2.000 to 8.500 HardCopy IV GX: 2.000 to 7.000 Stratix II GX: 2.000 to 6.375 |
0.600-3.125 |
| Basic Mode Channel Bonding | Yes | No | Yes | Yes | Yes (except Stratix II GX) |
Yes |
| Possible Reference Clock (MHz) | 50.0 to 622.08 | 25 to 650 | 50.0 to 622.08 | 50.0 to 622.08 | 50.0 to 622.08 | 5.0 to 472.5 |
| FPGA Bus Width (Bits) | 8,10,16,20 | 8,10, 16, or 20 | 16, 20, 32, 40 | 8, 10, 16, 20 | 16, 20, 32, 40 | 8, 10, 16, 20 |
| 8B/10B Encode/Decode |  |
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| Dedicated Synchronization State Machine | |
- | |
- | |
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| Word Align | |
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| Rate Match | |
- | |
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| Byte Serialize/ Deserialize | |
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| Phase Comp FIFO | |
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| Dynamic Reconfiguration | |
(1) |
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| Byte Ordering | |
- | |
- | |
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| Single Bit Slip | |
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- Limited to pre-emphasis, equalization, and VOD.
Tools
Basic mode is available as a transceiver configuration option within Quartus® II development software. Once you select basic mode, Quartus II software guides you through configuration options for each of the available blocks. Collateral is also available to support the basic transceiver modes, including a generic characterization report, user guides, transceiver simulation models, and design kits for industry-standard PCB and layout simulation tools.
Related links
- Stratix IV FPGA Family Overview
- HardCopy IV ASICs Family Overview
- Cyclone IV FPGA Family Overview
- Transceiver Overview: Stratix IV and HardCopy IV Devices
- Transceiver Overview: Arria II GX Devices
- Arria II GX FPGA Family Overview
- Stratix IV GX and HardCopy IV GX Physical Medium Attachment Layer
- Stratix IV GX and HardCopy IV GX Physical Coding Sublayer
- Stratix II GX FPGA Overview
- Transceiver Overview: Stratix II GX Devices
- Stratix II GX Physical Medium Attachment Layer
- Stratix II GX Physical Coding Sublayer
- Stratix GX Overview
- Stratix GX Multi-Gigabit Transceiver Block Technical Details
- SerialLite II
