Reduce Manufacturing Costs by Integrating Flash Device Programming

Standard flash memory devices are used in many applications to store configuration, program, or memory data. Before these flash devices can be used in a system, they must be programmed. Using traditional methods, programming can absorb large amounts of time in the manufacturing process and provide little flexibility for last-minute changes or programming updates while the product is in the field. 

Altera’s parallel flash loader solution addresses these issues, simplifying manufacturing processes, lowering costs, allowing for in-field updates, and providing other benefits.  The solution uses a MAX^® II CPLD to bridge the JTAG interface and the flash device’s parallel address/data interface. Instead of shifting data through all of the pins on the MAX II device, using Altera's parallel flash loader quickly retrieves data from the JTAG scan chain and generates data that is formatted for the receiving target flash device.

This solution significantly reduces flash device programming time. Using the example of programming a single vector into a 48-pin common flash interface (CFI) flash device, Table 1 shows the possible amount of time saved by using Altera's parallel flash loader solution. The example compares using the parallel flash loader solution to using the traditional method of programming via the JTAG boundary scan chain with a JTAG-compatible programmable logic device or application-specific integrated circuit (ASIC) that has about 200 pins.

For more information, read the Reduce Manufacturing Costs by Integrating Flash Device Programming White Paper (PDF).

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