Arria® II GX FPGA I/Os support a broad range of external memory interfaces, such as DDR3, DDR2, DDR, SDR SDRAM, and QDR II SRAM, as shown in Table 1. DDR3, DDR2, DDR, and SDR SDRAM are supported by a new self-calibrating datapath available as the ALTMEMPHY megafunction. This megafunction removes process variation and compensates for voltage and temperature variations to achieve data rates up to 600 Mbps, and also ease timing closure.
The Arria II GX I/O structure is based on the successful Cyclone® III I/O structure. For this reason, many of the Cyclone III FPGA documents referenced in Table 2 are also applicable to Arria II GX FPGAs.
| Table 1. Arria II GX FPGA Maximum Clock Rate Support for External Memory Interfaces | ||
| Memory Type | Maximum Data Rate (Per Pin) | Maximum Clock Frequency |
|---|---|---|
| DDR3 SDRAM | 600 Mbps | 300 MHz |
| DDR2 SDRAM | 600 Mbps | 300 MHz |
| DDR SDRAM | 400 Mbps | 200 MHz |
| SDR SDRAM | 300 Mbps | 150 MHz |
| QDR II SRAM | 500 Mbps | 250 MHz |
Table 2 lists resources and technical collateral for building external memory interfaces on Arria II GX FPGAs.
| Table 2. Arria II GX FPGA External Memory Resources | ||
| Collateral | Description | |
|---|---|---|
| External Memory Handbook | External memory interfaces including DDR, DDR2, DDR3, QDR II/+, and RLDRAM II provide caching or data storage space in the majority of end systems featuring FPGAs. | |
| IP MegaStoreTM Web Page | The web page links to different intellectual property (IP) cores provided by Altera and our partners. The web page also allows you to search for an IP core of your interest. | |
| External Memory Design Examples | The page contains design examples for developing external memory solutions on Altera® products. | |
| HSPICE Models | Web page providing board design-related resources for Altera devices. | |
| IBIS Models | Web page listing of all the IBIS models for Altera devices. | |
| Debug GUI User Guide | User guide for the debug GUI. | |
| Debug GUI | A .zip file that contains the debug GUI. | |
| External Memory Interfaces in Arria II GX Devices (PDF) | Describes device internals such as DDR memory interface pins, DQS phase-shift circuitry, and DDR registers. | |
| TimeQuest Resources | Provides links and resources to learn more about the TimeQuest timing analyzer. | |
| Board Design Guidelines Solution Center | Web page providing board design-related resources for Altera devices. | |
