The Cyclone® V FPGA I/Os support a broad range of external memory interfaces, such as DDR3, DDR2, DDR SDRAM, and QDR II SRAM as shown on the External Memory Interface Solutions Center page. DDR3, DDR2, DDR SDRAM, and QDR II SRAM are supported by a hard memory controller. The hard memory controller supports Altera's innovative UniPHY architecture, which supports the automatic deskew of DQ lines, and the new High Peformance Memory Controller II (HPMC II), which supports data reodering for high memory efficiency. The hard memory controller removes process variation and compensates for voltage and temperature variations to achieve data rates up to 800 Mbps, and also to ease timing closure.
Table 1 lists reference resources for additional information on Cyclone V FPGA external memory resources.
|Table 1. Cyclone V FPGA External Memory Resources|
|External memory handbook||Provides information on external memory interfaces. External memory interfaces including DDR, DDR2, DDR3, QDR II/+, and RLDRAM II provide caching or data storage space in the majority of end systems featuring FPGAs.|
|IP MegaStoreTM web page||Links to different intellectual property (IP) cores provided by Altera and our partners. Also allows you to search for an IP core of your interest.|
|External memory design examples||Contains design examples for developing external memory solutions on Altera® products.|
|HSPICE models||Provides resources related to board design for Altera devices.|
|IBIS models||Lists all of the IBIS models for Altera devices.|
|Debug GUI user guide||Is a user guide for the debug GUI.|
|Debug GUI||Is a .zip file that contains the debug GUI.|
|TimeQuest resources||Provides links and resources to learn more about the TimeQuest timing analyzer.|
|Board design guidelines solution center||Provides resources related to board design for Altera devices.|