The Stratix® IV FPGA I/O structure is based on the successful Stratix III FPGA I/O structure with its proven high-performance architecture. For this reason, many of the Stratix III documents referenced in Table 1 are directly applicable to Stratix IV FPGAs. The I/O structure itself is ideal for interfacing to existing and emerging external memory standards.
| Table 1. Stratix IV FPGA Maximum Clock Rate Support for External Memory Interfaces | ||
| Memory Type | Maximum Data Rate (Per Pin) | Maximum Clock Frequency |
|---|---|---|
| DDR3 SDRAM | 1,067 Mbps | 533 MHz |
| DDR2 SDRAM | 800 Mbps | 400 MHz |
| DDR SDRAM | 400 Mbps | 200 MHz |
| RLDRAM II | 800 Mbps | 400 MHz |
| QDR II+ SRAM | 1,600 Mbps | 400 MHz |
| QDR II SRAM | 1,400 Mbps | 350 MHz |
Table 2 lists resources and technical collateral for building external memory interfaces on Stratix IV FPGAs.
| Table 2. Stratix IV FPGA External Memory Resources | ||
| Collateral | Description | |
|---|---|---|
| External Memory Handbook | External memory interfaces including DDR, DDR2, DDR3, QDR II/+, and RLDRAM II provide caching or data storage space in the majority of end systems featuring FPGAs. | |
| IP MegaStoreTM Web Page | This web page links to different intellectual property (IP) cores provided by Altera and our partners. The web page also allows you to search for an IP core of your interest. | |
| External Memory Design Examples | This page contains design examples for developing external memory solutions on Altera products. | |
| HSPICE Models | Web page providing board design-related resources for Altera® devices. | |
| IBIS Models | Web page listing of all the IBIS models for Altera devices. | |
| Debug GUI User Guide (PDF) | User guide for the debug GUI. | |
| Debug GUI | A .zip file that contains the debug GUI. | |
| TimeQuest Resources | Provides links and resources to learn more about the TimeQuest timing analyzer. | |
| Board Design Guidelines Solution Center | Web page providing board design-related resources for Altera devices. | |
