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Stratix IV FPGA External Memory Resources

The Stratix® IV FPGA I/O structure is based on the successful Stratix III FPGA I/O structure with its proven high-performance architecture. For this reason many of the Stratix III documents referenced below are directly applicable to Stratix IV FPGAs. The I/O structure itself is ideal for interfacing to existing and emerging external memory standards (refer to Table 1).

Table 1. Stratix IV FPGA Maximum Clock Rate Support for External Memory Interfaces
Memory Type Maximum Data Rate (Per Pin) Maximum Clock Frequency
DDR3 SDRAM 1,067 Mbps 533 MHz
DDR2 SDRAM 800 Mbps 400 MHz
DDR SDRAM 400 Mbps 200 MHz
RLDRAM II 800 Mbps 400 MHz
QDRII+ SRAM 1,400 Mbps 350 MHz
QDRII SRAM 1,400 Mbps 350 MHz

Table 2 lists resources and technical collateral for building external memory interfaces on Stratix IV FPGAs.

Table 2. Stratix IV FPGA External Memory Resources
Collateral Description Key (1)
Start Here
AN 435: Design Guidelines for Implementing DDR & DDR2 SDRAM Interfaces in Stratix III Devices (PDF) Describes typical DDR and DDR2 SDRAM memory interface design flow for Stratix III devices. Also provides links to pertinent literature for each design step. A
AN 436: Design Guidelines for Implementing DDR3 SDRAM Interfaces in Stratix III Devices (PDF) Describes typical DDR3 SDRAM memory interface design flow for Stratix III FPGAs. Also provides links to pertinent literature for each design step. A
Device Selection
Selecting the Right High-Speed Memory Technology for Your System (PDF) Describes how to select the right memory for your application. A/L
The Efficiency of the DDR & DDR2 SDRAM Controller Compiler (PDF) Describes terminologies such as bandwidth, efficiency, and read latency. A/L
External Memory Interfaces in Stratix III Devices (PDF) Describes Stratix III device internals such as DDR memory interface pins, DQS phase-shift circuitry, and DDR registers. A
IP/Megafunction User Guides
DDR/DDR2 SDRAM High-Performance Controller User Guide (PDF) Describes the controller interface and the design flow using the MegaWizard® Plug-In Manager and ALTMEMPHY. A
ALTMEMPHY Megafunction User Guide (PDF) Describes the ALTMEMPHY megafunction functionality and how to interface with Altera’s DDR and DDR2 SDRAM high-performance controllers and third-party controllers. A
IP MegaStoreTM Web Page The web page links to different intellectual property (IP) cores provided by Altera and their partners. The web page also allows you to search for an IP of your interest. A/L
Timing Analysis
AN 438: Constraining & Analyzing Timing for External Memory Interfaces in Stratix III Devices (PDF) Describes the various timing related paths, constraints, and analysis used by the ALTMEMPHY megafunction in Stratix III designs. A
TimeQuest Timing Analyzer (PDF) Learn about the features of the TimeQuest timing analyzer and how to constrain your design with SDC commands. A/L
TimeQuest Resources Provides links and resources to learn more about the TimeQuest timing analyzer. A/L
Models and Board Design Guidelines
AN 444: Dual DIMM DDR2 SDRAM Memory Interface Design Guidelines (PDF) Describes the design guidelines for developing a dual DIMM DDR2 SDRAM memory interface. A/L
Board Design Guidelines Solution Center Web page providing board design-related resources for Altera® devices. A/L
HSPICE Models Web page listing of all the HSPICE models for Altera devices. A/L
IBIS Models Web page listing of all the IBIS models for Altera devices. A/L

Notes:

  1. L = Legacy core. DDR and DDR2 SDRAM Controller MegaCore® function
    (integrated static datapath and controller solution)
  2. A = New auto-PHY solution delivered via the ALTMEMPHY megafunction

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