External Memory Solutions Center—DDR2 SDRAM
Obtain up to 400-MHz (800 Mbps) DDR2 SDRAM operation with Altera’s new, self-calibrating, altmemphy PHY interface megafunction. altmemphy calibrates out process variation and much more (see Tables 1 and 2).
| Table 1. altmemphy Megafunction with DDR2 SDRAM High-Performance Controller (New Auto-PHY with Separate Controller) |
| Data Rate (Mbps) |
Frequency (MHz) |
Supporting FPGAs |
| 800 (1) |
400 (1) |
Stratix® III |
| 667 |
333 |
Stratix III, Stratix II, Stratix II GX |
| 400 |
200 |
Stratix III, Stratix II, Stratix II GX,
Cyclone® III |
| 333 |
167 |
Stratix III, Stratix II, Stratix II GX,
Cyclone III |
| 200 |
100 |
Stratix III, Stratix II, Stratix II GX,
Cyclone III |
Note:
- Pending characterization.
Table 2. DDR2 SDRAM Controller MegaCore® Function
(Legacy Integrated Static Datapath and Controller) |
| Data Rate (Mbps) |
Frequency (MHz) |
Supporting FPGAs |
| 533 |
267 |
Stratix II, Stratix II GX, HardCopy® II |
| 400 |
200 |
Stratix II, Stratix II GX, HardCopy II |
| 333 |
167 |
Stratix II, Stratix II GX, HardCopy II, Cyclone II |
| 200 |
100 |
Stratix II, Stratix II GX, HardCopy II, Cyclone II |
Selecting The Appropriate Core
For more information on when to use the new altmemphy megafunction and controller versus the legacy static-timing combined PHY and controller intellectual property (IP) core, refer to External Memory Interface Options for Stratix II Devices (PDF).
More About the altmemphy Megafunction
Altera developed a dynamic, self-calibrating datapath altmemphy megafunction that removes process variation and compensates for voltage and temperature variations to achieve up to 400-MHz DDR2 performance.
The altmemphy megafunction takes full advantage of the Stratix II, Stratix II GX, Stratix III, and Cyclone III device I/O structures and reconfigurable phase-locked loops (PLLs). It uses a training pattern and calibration to remove any process variation in both the FPGA and memory device. Additionally, it uses a tracking mechanism during operation to track and compensate for any voltage or temperature variations within the FPGA without interrupting the data transfer.
The PHY (altmemphy) and associated controller (DDR SDRAM high-performance controller) are two distinct products. The legacy DDR SDRAM controller MegaCore function is an integrated PHY and controller solution. The rationale behind this decision to split the PHY interface and controller for the newer products is to enable you and third-party IP providers to design specialized controllers, while still benefiting from the Altera® PHY interface.
The PHY interface (altmemphy), which comprises silicon features as well as soft logic, is responsible for the safe transfer of data between the FPGA and the memory, including all aspects of crossing between different clock domains. The memory controller IP is fully synchronous logic that translates between the application domain and the memory domain, handling cycle-by-cycle timing issues.
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