Obtain up to 400-MHz (800 Mbps) DDR2 SDRAM operation with Altera’s self-calibrating ALTMEMPHY PHY interface megafunction. ALTMEMPHY calibrates out any process variation and much more (see Tables 1 and 2).
| Table 1. ALTMEMPHY Megafunction with DDR2 SDRAM High-Performance Controller (Auto-PHY with Separate Controller) | ||
Data Rate (Mbps) |
Frequency |
Supporting Devices |
|---|---|---|
| 800 | 400 | Stratix® IV, Stratix III |
| 667 | 333 | Stratix IV, Stratix III, Stratix II, Stratix II GX, HardCopy® IV, HardCopy III |
| 600 | 300 | Stratix IV, Stratix III, Stratix II, Stratix II GX, HardCopy IV, HardCopy III, Arria® II GX |
| 533 | 267 | Stratix IV, HardCopy IV, HardCopy III, Arria II GX, HardCopy II |
| 400 | 200 | Stratix IV, Stratix III, Stratix II, Stratix II GX, HardCopy IV, HardCopy III, HardCopy II, Arria II GX, Cyclone® IV GX, Cyclone III |
| 333 | 167 | Stratix IV, Stratix III, Stratix II, Stratix II GX, HardCopy IV, HardCopy III, HardCopy II, Arria II GX, Cyclone IV E, Cyclone III, Cyclone III LS |
| 200 | 100 | Stratix IV, Stratix III, Stratix II, Stratix II GX, Arria II GX, Cyclone IV, Cyclone III, Cyclone III LS |
| Table 2. DDR2 SDRAM Controller MegaCore Function (Legacy Integrated Static Datapath and Controller) | ||
| Data Rate (Mbps) | Frequency (MHz) |
Supporting Devices |
|---|---|---|
| 533 | 267 | Stratix II, Stratix II GX, HardCopy II |
| 400 | 200 | Stratix II, Stratix II GX, HardCopy II |
| 333 | 167 | Stratix II, Stratix II GX, HardCopy II, Cyclone II |
| 200 | 100 | Stratix II, Stratix II GX, HardCopy II, Cyclone II |
About the ALTMEMPHY Megafunction
Altera's dynamic, self-calibrating datapath ALTMEMPHY megafunction removes process variation and compensates for voltage and temperature variations to achieve up to 400-MHz DDR2 performance.
The ALTMEMPHY megafunction takes full advantage of the Stratix IV, Stratix III, Stratix II, Stratix II GX, Arria II GX, Cyclone IV, Cyclone III, and Cyclone III LS FPGA I/O structures and reconfigurable phase-locked loops (PLLs). It uses a training pattern and calibration to remove any process variation in both the FPGA and memory device. Additionally, it uses a tracking mechanism during operation to track and compensate for any voltage or temperature variations within the FPGA without interrupting the data transfer.
The PHY (ALTMEMPHY) and associated controller (DDR SDRAM high-performance controller) are two distinct products. The legacy DDR SDRAM controller MegaCore® function is an integrated PHY and controller solution. The rationale behind this decision to split the PHY interface and controller for the newer products is to enable you and third-party intellectual property (IP) providers to design specialized controllers, while still benefiting from the Altera® PHY interface.
The PHY interface (ALTMEMPHY), which comprises silicon features as well as soft logic, is responsible for the safe transfer of data between the FPGA and the memory, including all aspects of crossing between different clock domains. The memory controller IP is fully synchronous logic that translates between the application domain and the memory domain, handling cycle-by-cycle timing issues.
Selecting the Appropriate Core
For more information on when to use the ALTMEMPHY megafunction and controller versus the legacy static-timing combined PHY and controller IP core, refer to the External Memory PHY Interface Megafunction User Guide (ALTMEMPHY) (PDF).
