Memory Solutions Center—DDR3 SDRAM
To obtain up to 533-MHz DDR3 performance on Stratix® III FPGAs and up to 400 MHz(1) performance on HardCopy® III ASICs across process, voltage, and temperature, Altera developed a dynamic self-calibrating PHY megafunction known as altmemphy.
As shown in Figure 1, the altmemphy datapath megafunction takes full advantage of the DDR3 optimized I/O structures in Stratix III FPGAs and HardCopy III ASICs, which include read and write leveling functionality, I/O delay for DQ de-skew, and the use of a reconfigurable phase-locked loop (PLL) to compensate for voltage and temperature variations. At start up, altmemphy uses a training pattern to perform calibration, removing any process variation in both the Altera® device and the memory device. During operation, a tracking mechanism tracks and compensates for any voltage or temperature variations within the Altera device without interrupting the data transfer.
Figure 1. Dynamic Self-Calibrating PHY Megafunction Optimized for DDR3 SDRAM
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Altera has also taken the step to separate the physical interface and the controller into two distinct products. This enables you and third-party intellectual property (IP) providers to design specialized controllers, while still gaining all the benefits of Altera's physical interface.
The Altera physical interface, which comprises silicon features as well as soft logic, is responsible for the safe transfer of data between the Altera device and the memory, including all aspects of crossing between different clock domains. The memory controller IP is fully synchronous logic that translates between the application domain and the memory domain, handling cycle-by-cycle timing issues.
Visit the Stratix III External Memory Resources Center for application notes, timing closure tools, design guidelines, and more.
Note:
1. HardCopy performance depends on design and pending silicon characterization results
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