To obtain up to 533-MHz DDR3 performance over process, voltage, and temperature, Altera has developed a dynamic self-calibrating PHY megafunction known as ALTMEMPHY.
As shown in Figure 1, the ALTMEMPHY datapath megafunction takes full advantage of the DDR3-optimized I/O structures in Stratix® IV and Stratix III FPGAs and HardCopy® IV and HardCopy III ASICs, which include read and write leveling functionality, I/O delay for DQ de-skew, and the use of a reconfigurable phase-locked loop (PLL) to compensate for voltage and temperature variations. For Arria® II GX FPGAs, these features exist within ALTMEMPHY, providing a cost-optimized, fully-featured memory interface solution. At start up, ALTMEMPHY uses a training pattern to perform calibration, removing any process variation in both the FPGA and memory device. Additionally, it uses a tracking mechanism during operation to track and compensate for any voltage or temperature variations within the FPGA without interrupting the data transfer.
Figure 1. Dynamic Self-Calibrating PHY Megafunction Optimized for DDR3 SDRAM
Altera has also taken the step to separate the physical interface and the controller into two distinct products. This enables you and third-party intellectual property (IP) providers to design specialized controllers, while still gaining all the benefits of Altera's physical interface.
The Altera® physical interface, which comprises silicon features as well as soft logic, is responsible for the safe transfer of data between the FPGA or HardCopy ASIC and the memory, including all aspects of crossing between different clock domains. The memory controller IP is fully synchronous logic that translates between the application domain and the memory domain, handling cycle-by-cycle timing issues.
Visit the Arria II GX, Stratix III, and Stratix IV external memory resource centers for application notes, timing closure tools, design guidelines, and more.
