Memory Solutions Center—DRAM Devices Overview
Dynamic random access memory (DRAM) devices are volatile memories offering a lower cost per bit than SRAM devices. A compact memory cell consisting of a capacitor and a transistor makes this possible over the six-transistor cell used in SRAM. However, the capacitor will discharge, causing the memory cell to lose its state, which means that DRAM memory needs to be refreshed periodically. Generally, designers choose SRAM devices for applications where latency or low interface complexity is important. They choose DRAM where cost per bit is important. Special types of DRAM challenge this norm by offering improved random access latency as well as a lower cost per bit.
Altera provides complete system solutions to help memory designers successfully interface Altera® FPGAs to a variety of DRAM devices.
DDR SDRAM
Double data rate (DDR) SDRAM is an evolution of single data rate (SDR) SDRAM. It offers higher performance through increased bus speeds using a lower I/O voltage (2.5 V), and most importantly, data transfer on both clock edges, doubling the raw bandwidth. DDR SDRAM is a widely established memory technology. It offers the lowest cost per bit, due in part to its broad acceptance in almost any marketplace.
DDR2 SDRAM
DDR2 SDRAM is an evolution of DDR SDRAM. It operates using a lower voltage (1.8 V). DDR2 offers increased densities and even higher performance through higher bus speeds and an optimized interface. The advantages of DDR2 architecture over DDR are summarized as follows:
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Speed - Data rate ranges 400 Mbps ~ 667 Mbps
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Power - Lower than DDR SDRAM due to reduced I/O voltage and core voltage
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Size - FBGA packages provide smaller footprints
RLDRAM II
Reduced latency DRAM II (RLDRAM II) is the second generation of RLDRAM. It is a development of DDR SDRAM, designed to address the low latency requirements of certain applications, such as packet buffers in high-performance line cards. RLDRAM II has a high-performance DDR data bus and offers a non-multiplexed address bus, reducing the number of clock cycles to initiate read or write applications. A banked architecture also reduces access time. In some systems, RLDRAM II eliminates the need for specialized content-addressable memory (CAM) or SRAM.
SDR DRAM
Single data rate (SDR) SDRAM is the first generation of synchronous DRAM. It improves memory bandwidth over extended data out (EDO) DRAM by offering data transfer up to once-per-clock cycle.
DRAM Memory Vendors
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