Memory System Hardware Test Results – RLDRAM II & Stratix FPGAs
This web page provides a summary of hardware test results for Stratix® FPGAs interfacing with reduced latency dynamic random access memory II (RLDRAM II) memory devices.
Highlights from the test results include:
- Hardware-proven system performance exceeds 400 Mbps data rate (200 MHz clock frequency) with Stratix FPGAs.
- Measurement waveforms correlate well with simulation waveforms.
Memory System Test Environment
Table 1 displays the test parameters for Stratix FPGAs interfacing with the RLDRAM II memory devices.
|
Table 1. Experiment Setup for Stratix & RLDRAM II System Test
|
|
Test Parameter
|
Description
|
|
Test Board
|
RLDRAM II Stratix Hardware Reference Platform
|
| Stratix Device |
EP1S40F1020-5 |
| Memory Device |
Micron RLDRAM II CIO MT49H16M18FM-2.5 |
| Memory Interface I/O |
HSTL 1 |
Board Setup
The RLDRAM II Stratix Hardware Reference Platform includes the following: one Stratix EP1S40F1020 device, two 16 Meg x 18 bit RLDRAM II CIO devices (located on the top banks of the Stratix FPGA), configuration devices, standard expansion ports, buttons, switches, LEDs, debug ports for logic analyzer connectors, and characterization components.
The following photo is this RLDRAM II Stratix Hardware Reference Platform.
Block Diagram
Altera thoroughly tested the Stratix RLDRAM II memory interface solution on the hardware platform. The following figure shows a top-level block diagram of the system.
Figure 1. Block Diagram of RLDRAM II Memory Controller on a Stratix Device
Note
(1) Stratix devices do not use QK# for read operations
Test Results
Test results found the following:
- The RLDRAM II controller implemented on a Stratix FPGA exceeds the performance of 400 Mbps (200 MHz clock frequency). Shown in figure 2.
- Actual hardware measurement results correlated to the simulation results.
Figure 2. RLDRAM II CIO Single Bit Data Eye Diagram - 200 MHz
Conclusion
RLDRAM II memory is a new high-density, high-performance SRAM-like random access for performance-critical networking and cache applications. The hardware test results from interfacing Altera's Stratix devices with RLDRAM II memory devices show how Altera FPGA devices can reduce time-to-market and provide low-risk for new design implementation.
Contact your local Altera Field Applications Engineer (FAE) for a demonstration.
Related Links
|
Literature
> 
