Altera has developed a dynamic, self-calibrating datapath ALTMEMPHY megafunction that removes process variation and compensates for voltage and temperature variations to obtain maximum margin (see Tables 1 and 2).
| Table 1. ALTMEMPHY Megafunction with DDR SDRAM High-Performance Controller (Auto-PHY with Separate Controller) | ||
| Data Rate (Mbps) | Frequency (MHz) |
Supporting Devices |
|---|---|---|
| 400 | 200 | Stratix® IV, Stratix III, Stratix II, Stratix II GX, HardCopy® IV, HardCopy III, HardCopy II, Arria® II GX, Arria GX, Cyclone® IV, Cyclone III |
| Table 2. DDR SDRAM Controller MegaCore Function (Legacy Integrated Static Datapath and Controller) | ||
| Data Rate (Mbps) | Frequency (MHz) |
Supporting Devices |
|---|---|---|
| 400 | 200 | Stratix II, Stratix II GX, Stratix, HardCopy II, Cyclone II, Cyclone |
Selecting the Appropriate Core
For more information on when to use the new ALTMEMPHY megafunction and controller versus the legacy static-timing combined PHY and controller intellectual property (IP) core, refer to External Memory Interface Options for Stratix II Devices (PDF).
More About the ALTMEMPHY Megafunction
The ALTMEMPHY megafunction takes full advantage of the Stratix IV, Stratix III, Stratix II, Stratix II GX, Arria II GX, Arria GX, Cyclone IV, and Cyclone III device I/O structures and reconfigurable phase-locked loops (PLLs). It uses a training pattern and calibration to remove any process variation in both the FPGA and memory device. Additionally, it uses a tracking mechanism during operation to track and compensate for any voltage or temperature variations within the FPGA without interrupting the data transfer.
The PHY (ALTMEMPHY) and associated controller (DDR SDRAM high-performance controller) are two distinct products. The legacy DDR SDRAM controller MegaCore® function is an integrated PHY and controller solution. The rationale behind this decision to split the PHY interface and controller for the newer products is to enable you and third-party IP providers to design specialized controllers, while still benefiting from the Altera® PHY interface.
The PHY interface (ALTMEMPHY), which comprises silicon features as well as soft logic, is responsible for the safe transfer of data between the FPGA and the memory, including all aspects of crossing between different clock domains. The memory controller IP is fully synchronous logic that translates between the application domain and the memory domain, handling cycle-by-cycle timing issues.
