QDR II SRAM devices enable you to maximize memory bandwidth with separate read and write ports. The QDR II architecture features two data ports operating twice per clock cycle to deliver a total of four data instructions per cycle. The resulting performance increase is particularly valuable in bandwidth-intensive applications such as main memory for look-up tables (LUTs), linked lists, and controller buffer memory.
QDR II and QDR II+ devices offer significant benefits over QDR devices, including higher performance, increased data valid time, simplified data capture, a guaranteed relationship between clock rate and data rate, and an overall ease-of-design. QDR II SRAM vendor websites contain more information on the benefits of QDR II devices.
Table 1 lists QDR II/QDR II+ SRAM memory interface performance support in Altera® FPGAs and HardCopy® ASICs.
| Table 1. QDR II/QDR II+ SRAM Memory Interface Performance Support in Altera Devices | |
| Device | Maximum QDR II/QDR II+ SRAM Interface Performance |
|---|---|
| Stratix® IV | 1.6 Gbps (1) (400 MHz) |
| Stratix III | 1.6 Gbps (1) (400 MHz) |
| Stratix II | 1 Gbps (1) (250 MHz) |
| Stratix II GX | 1 Gbps (1) (250 MHz) |
| Stratix | 800 Mbps (200 MHz) |
| Stratix GX | 800 Mbps (200 MHz) |
| Arria® II GX | 1 Gbps (1, 2) (250 MHz) |
| Cyclone® IV | 667 Mbps (167 MHz) |
| Cyclone III | 667 Mbps (167 MHz) |
| Cyclone III LS | 300 Mbps (150 MHz) |
| Cyclone II | 667 Mbps (167 MHz) |
| HardCopy IV | 1.4 Gbps (1, 2) (350 MHz) |
| HardCopy III | 1.4 Gbps (1, 2) (350 MHz) |
| HardCopy II | 1 Gbps (1) (250 MHz) |
Notes:
- For both read and write ports
- Subject to characterization
Technical Documentation
Altera offers the following technical documentation that contains information on device support for the QDR and QDR II memory interfaces, as shown in Table 2.
Software Support and Tools
Altera offers the tools shown in Table 3 to aid in the QDR II and QDR II+ SRAM memory interface design process.
| Table 3. QDR II SRAM Software and Support Tools | |
| Feature | Applicable Devices |
|---|---|
| TimeQuest Timing Analyzer | All |
| IBIS Models for I/O Buffers | All |
IP Cores and Reference Designs
Table 4 lists QDR II SRAM controller intellectual property (IP) cores and reference designs available from Altera.
| Table 4. QDR II SRAM IP Cores and Reference Designs | |||
| Controller Name | Free Evaluation | Vendor | Devices Supported |
|---|---|---|---|
| QDR II SRAM Controller MegaCore® Function | Yes | Altera | Stratix III, Stratix II, Stratix II GX, Stratix, Stratix GX, HardCopy III, HardCopy II |
Development Kits and Hardware Reference Platforms
Table 5 lists memory hardware reference platforms available from Altera. The Gerber files, layout, termination recommendations, and signal integrity analysis information of these reference platforms are also available.
| Table 5. QDR II SRAM Development Kits and Hardware Reference Platforms | ||
| Board Name | Vendor | Contact Information |
|---|---|---|
| QDR II SRAM Stratix Memory Reference Platform | Altera | Contact Altera or your local Altera FAE |
QDR II SRAM Vendors
Related Links
- Stratix IV Device I/O Connectivity
- Stratix III Device I/O Connectivity
- External Memory Device Interfaces in Stratix II, Stratix, and Stratix GX FPGAs
- External Memory Device Interfaces in Cyclone II and Cyclone FPGAs
- External Memory Interfaces in Cyclone IV Devices (PDF)
- External Memory Device Interfaces in APEX™ II Devices
- Altera's Signal Integrity Center
