Parallel I/O

Altera provides a comprehensive I/O interface solution with support for a variety of single-ended and differential I/O standards, external memory, and high-speed interfaces to meet your high-bandwidth system requirements.

	Devices
Stratix® IV FPGA Stratix IV I/O Connectivity Single-Ended I/O Standards Dynamic On-Chip Termination External Memory Device Interfaces  HardCopy® IV ASIC HardCopy IV I/O Connectivity Stratix III FPGA Stratix III I/O Connectivity Single-Ended I/O Standards Dynamic On-Chip Termination Stratix II GX FPGA Source-Synchronous Signaling Source-Synchronous Protocols Single-Ended I/O Standards External Memory Device Interfaces On-Chip Termination Stratix II FPGA Source-Synchronous Signaling Source-Synchronous Protocols Single-Ended I/O Standards External Memory Device Interfaces On-Chip Termination Stratix GX FPGA Source-Synchronous Signaling Source-Synchronous Protocols System Applications Single-Ended I/O Standards External Memory Device Interfaces On-Chip Termination Stratix FPGA Differential and Single-Ended I/O Standards High-Speed Interfaces External Memory Device Interfaces On-Chip Termination Arria® II GX FPGA I/O Features in Arria II Devices (PDF) External Memory Interfaces in Arria II GX Devices (PDF) High-Speed Differential I/O Interfaces With DPA in Arria II Devices (PDF) Arria GX FPGA High-Speed, Source-Synchronous Differential I/O Interface (PDF)  Selectable I/O Standards in Arria GX Devices (PDF)  External Memory Interfaces in Arria GX Devices (PDF)  Cyclone® IV FPGA  I/O Features in Cyclone IV Devices (PDF) External Memory Interfaces in Cyclone IV Devices (PDF) Cyclone III FPGA Cyclone III I/O Connectivity On-Chip Termination External Memory Device Interfaces Cyclone II FPGA Cyclone II I/O Support Cyclone II Interfaces and Protocol Support External Memory Device Interfaces On-Chip Termination Cyclone FPGA Differential and Single-Ended I/O Standards External Memory Device Interfaces
	Software
Quartus® II Software
	Protocols and Intellectual Property
SPI-4.2 RapidIO® Standard HyperTransport™ Standard Communications Intellectual Property (IP) Cores Interfaces and Peripherals IP Cores Digital Signal Processing (DSP) IP Cores Embedded Processors IP Cores
	Design Examples
Bus and I/O Design Examples
	Literature
IP Communications Literature Interfaces and Peripherals Literature
	Training
Altera® Technical Training Courses Interfacing to External Memory With Altera FPGAs Using High-Performance Memory Interfaces in Altera FPGAs Constraining and Analyzing Double Data Rate Source-Synchronous Interfaces Constraining and Analyzing Timing for Source-Synchronous Circuits With TimeQuest Timing Analyzer Stratix III Devices: Features and Capabilities Serial RapidIO Design With Stratix IV GX FPGAs PCI Express Design with Altera 40-nm Devices 10/100/1000 Mb and 10Gb Ethernet Design with Altera 40-nm Devices High-Speed Serial Protocol Design with Altera 40-nm Devices Dynamically Reconfiguring Stratix II GX Transceivers
	Support
Board Design Guidelines Solution Center Online Technical Support