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16 EMC Rules

Home > Technology > Signal Integrity > 16 EMC Rules

By Dr. Eric Bogatin
www.BeTheSignal.com

March 2007

More than 10 years ago, the Electromagnetic Compatibility Lab (EMC) at the University of Missouri at Rolla (UMR) developed a set of board-level design rules that, if followed, maximize the chance of a product passing an EMC certification test. Two companies created commercial “expert systems” tools based on these rules: Mentor Graphics’ Quiet Expert and Zuken’s CADSTAR EMC Advisor.

Recently, IBM entered the game with the release of their new tool EMSAT, taking the EMC board design rules to the next generation. Though many of the IBM design rules are also on the UMR list, Dr. Bruce Archambeault, one of IBM’s EMC guru’s says, “What makes them useful is that IBM (and sometimes UMR) has spent considerable time validating that these are the most IMPORTANT rules.”

As he indicates, some popular rules, such as the 20H rule, are not valid and may pose more of a distraction than a benefit.

Every board design is custom. Each board design has its own set of tradeoffs between the performance goals and the cost, risk, and schedule targets, including all the constraints about corporate culture and preferred vendors. It’s not possible to take a common set of rules and follow them blindly for every board. You end up with a system that may meet the performance requirements, but is too expensive to meet the cost targets.

While it is straightforward to perform critical net- and system-level circuit simulations to predict the signal integrity performance of a product before it is built, this is not the case for EMC analysis. Accurately simulating the radiated emissions of a complete product is too complex a problem to solve with today’s software and hardware tools.

That’s why it takes an expert to make those important tradeoffs between what you can afford and still have the system work the first time. With too many unique products and not enough experts, there is a problem. Enter EMC expert systems. IBM’s EMSAT applies a set of 16 rules to a board design to provide guidance about the potential landmines the design might encounter.

Every design rule has to be quantified. It’s in selecting the acceptable values for a component, a dimension, or a keep-out zone where the expert behind the expert system plays a critical role. That’s what you pay for when you purchase a commercial tool. However, just being aware of what the landmines are while you are designing your system can sometimes improve your chance for success.

With permission from Moss Bay EDA, distributors of IBM’s EMSAT, here is a brief summary of the 16 IBM design guidelines for good EMC design.

  1. Critical nets must not cross a split in the adjacent reference plane.
  2. Critical nets must not change reference planes.
  3. Critical nets may not be within a specified distance of the edge of their reference plane.
  4. Critical nets may not be routed within a specified distance from an I/O net.
  5. All critical nets must be buried between solid planes. The allowable length of the exposed portion of a critical net may be specified.
  6. All critical nets must have a "ground-guard" trace on either side of the critical net.
  7. All differential critical nets must have a "ground-guard" trace on either side of the differential pair of nets.
  8. All differential critical nets must be routed within a specified distance of each other, and the length of the differential pair of nets must match within a specified amount.
  9. All power and ground traces longer than a specified distance must be wider than another specified distance. This does not include grounded guard traces.
  10. Decoupling capacitors must be placed between all adjacent plane pairs within a specified grid density.
  11. A decoupling capacitor must be connected between the power and ground-reference planes and be placed within a specified distance from each IC power pin.
  12. The trace connecting between the IC power and/or ground reference pin to the associated via to the power/ground-reference plane must be no longer than the specified distance.
  13. The trace connecting between a decoupling capacitor to the associated via to the power/ground-reference plane must be no longer than the specified distance.
  14. All power and ground-reference traces longer than a specified length must have a decoupling capacitor within a specified distance from the IC power pin.
  15. All I/O filters must be placed within a specified distance from the I/O connector.
  16. All oscillators must be placed within a specified distance from the clock driver (or other device) that they drive.

For more information on EMC EMSAT, please visit www.MossBayEDA.com.

This and other signal integrity topics are covered in Eric’s public classes and online lectures, available from his website, www.BeTheSignal.com. Send your signal integrity technical questions to DoctorIsIn@BeTheSignal.com.

Be the signal logo

Bio: Eric Bogatin is president of Bogatin Enterprises. Many of his papers are available on his website, www.BeTheSignal.com. He is the author of Signal Integrity - Simplified, published by Prentice Hall.

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