By Dr. Eric Bogatin
www.BeTheSignal.com
May 2007
"I've traveled around the world and talked to hundreds of electronics companies and I keep hearing three common business drivers: reduce time to market by 50 percent, increase productivity by 30 percent, and design more competitive products." With these remarks, Henry Potts, Vice President and General Manager of the System Design Division of Mentor Graphics® opened his keynote address at the 2007 PCB Design West conference in Santa Clara on March 27.
He went on to suggest that innovation was the essential element to meeting these goals, with three key ingredients. The first ingredient is design process improvements in hardware technologies such as advanced ICs, FPGAs, and PCBs. The second is innovation in the infrastructure to support efficient designs using these technologies. Finally, he said, are advances in the EDA framework that enable collaboration across the “Global Enterprise,” which can span continents and time zones.
As an example of the trend in new PCB technologies, he offered data from Prismark comparing the $40B PCB fabrication industry in 2000 with the $45B industry today. While the total market size increased only 12 percent over 6 years, the percentage of micro via boards increased from 5.1 percent to 12.4 percent of the total market, driven by cell phones and other portable, wireless consumer products.
These remarks were the prelude to announcing the winners of the 19th Annual Technology Leadership Awards, a program sponsored by Mentor Graphics. Each year, completed, functional printed circuit designs are submitted in six categories from around the world. The only condition for submittal is that they are designed using a Mentor EDA tool. According to company representatives, it is "the longest running competition of its kind for PCB designers in the EDA industry."
In this respect, entries to the Technology Leadership Award program represent a snapshot sampling of designs for the current year and provide a rough metric of the trends in the industry. The common theme to all the past years has been increasing complexity and leveraging new PCB technologies. "Over the past few years, I have seen exponential growth in both the quality and the complexity of the designs," Pete Waddell, president of UP Media and one of the judges commented.
This year's winning companies were IBM Zurich Research Laboratory, Siemens, Qualcomm, Gage Applied Technologies, AVL List, Fujitsu Siemens Computers, and L-3 Communications.
Harry Potts identified six key metrics of complexity and how the submitted designs have evolved in just the past two years. Designs with at least one FPGA increased from 55 percent of entries in 2004 to 88 percent of entries in 2006. The average number of pins per PCB doubled, from 7,760 in 2004 to 14,666 in 2006. The average number of components placed on a board increased 37 percent, from 1,980 in 2004 to 2,711 in 2006.
The number of nets per board increased by 30 percent in the last two years, from 8,446 to 10,393. Of these, the number of high-speed or critical nets increased from 39 percent of all nets on a board in 2004 to nearly 88 percent of all nets on a board in the designs submitted in 2006.
Of the designs submitted, the maximum layer count was 28 in 2004, but 32 in 2006, with a proportional increase in the average number of layers used in designs. The maximum via density, as measured by pins per square inch, increased over 50 percent in the last two years, from about 700 pins per square inch to 1,100 pins per square inch in this year's submissions.
One way of demonstrating the complexity of a board is by comparing the average number of mounted components per square inch on the board to the average number of pins per component. Their product is the number of pins per square inch on the board. Typically, each pin requires at least one via connection, and often two or three to provide routing. For a given board, the average number of pins per component plotted against the component density is a map of interconnect density.
Mentor Graphics uses as a rough metric a constant product of 100 pins per square inch as the upper end of complexity, where through-hole technology is cost effective, and about 150 pins per square inch where HDI (high density interconnect) technology becomes cost effective.
When the designs submitted in the 2006 program are plotted on this graph, as shown in Figure 1, the distribution is clearly in the HDI regime. It is surprising that this applies to not just consumer electronics and high-end server applications, but also to the majority of the industrial control designs.
Figure 1. Technology Leadership Program Entries
The snapshot glimpse into the last few years of PCB design entries dramatically demonstrates the treadmill-like advance of product complexity. Potts indicated this will only continue and companies that want to compete must evolve and adapt to these changes by embracing innovation.
He concluded his keynote with a quote from Deloitte’s Mastering Innovation report: "Over the next six years, more than 70 percent of today's products will be obsolete."
This and other signal integrity topics are covered in Eric’s public classes and online lectures, available from his website, www.BeTheSignal.com. Send your signal integrity technical questions to DoctorIsIn@BeTheSignal.com.
Bio: Eric is president of Bogatin Enterprises, whose mission is to set the standard for signal integrity training. He is the author of Signal Integrity - Simplified, published by Prentice Hall. Check out his public signal integrity classes posted on www.BeTheSignal.com. He can be reached at eric@BeTheSignal.com.
