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| Archive | |
| "It Is Vanity to Do With More That Which Can Be Done With Less" September 2007 The mantra of the electronics packaging industry used to be “faster, denser, cheaper, NOW!” These driving forces fueled the development and introduction of the five most important packaging technology revolutions of the last 10 years. |
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| Don't Breathe Too Hard August 2007 High-speed serial links are fragile. You have to worry about tiny vias that might make up less than 1 percent of the total path length. You have to worry about the size, shape, and orientation of the glass weave in the laminate. You have to worry about the surface roughness of the copper. You have to worry about the size and location of the via clearance holes in the copper planes near the connectors. All of these delicate adjustments must be just right for a successful design. Now there’s a new worry. |
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The Shape of Things to Come? July 2007 |
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| Got 12 Ports? June 2007 It is often said, "Everything you ever wanted to know about a differential channel is contained in its 4-port differential S-parameters.” While this is perfectly true, it is not enough. In long backplane channels, which are strongly dominated by losses, crosstalk may pose the limitation to receiving the highest bit rate. This effect is not detectable with 4-port S-parameters in the standard configuration. |
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| Embrace Innovation to Survive May 2007 “I’ve traveled around the world and talked to hundreds of electronics companies and I keep hearing three common business drivers: reduce time to market by 50 percent, increase productivity by 30 percent, and design more competitive products.” |
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| Weave and Skew April 2007 The use of high-speed serial links in excess of 2.5 Gbps has accelerated since the turn of this century. Design principles for differential impedance, via stubs, conductor losses, and dielectric losses have been well established. |
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| 16 EMC Rules March 2007 More than 10 years ago, the Electromagnetic Compatibility Lab (EMC) at the University of Missouri at Rolla (UMR) developed a set of board-level design rules that, if followed, maximize the chance of a product passing an EMC certification test. |
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| Moving Toward the Transparent Connector February 2007 The higher the bit rate, the more problems connectors introduce. This article describes two technology options that may offer building blocks that can shift the connector design paradigm from pin-in-box to pad-to-pad and approach an electrically transparent connector. |
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| Automated TDR Testing January 2007 The board is finally back from fab. You power it on for the first time and find your sensitive LVDS line, has 30 mV too much noise, and its coming from a CMOS level control line running at 3.3v. The noise is only 1% of the control line voltage, but... |
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| Read other articles by Dr. Bogatin | |


