Arria® II GX 40-nm FPGAs simplify the challenges of designing for signal integrity by providing transceivers with best-in-class jitter characteristics. Advanced features in these transceivers simplify PCB design and compensate for inevitable board losses through multi-tap pre-emphasis, programmable VOD, and on-chip termination (see Table 1). Additional features are also included that enhance the die and package of the Arria II GX FPGA, resulting in excellent signal and power integrity and maximum user flexibility.
Figure 1. 40-nm Eye Diagram at 3.75 Gbps
Pre-emphasis, equalization, and VOD are all programmable in Arria II GX FPGAs. This allows you to change levels while the transceiver is operating, making it simpler to tune the interface for interoperability testing or to change a setting, depending on a board's location in a system. Tables 2 and 3 highlight the benefits of the I/O and packaging features and high-speed differential signals of Arria II GX FPGAs.
|Table 2. I/O and Packaging Features for Optimal Signal Integrity|
|8:1:1/2 User I/O, Ground and Power Ratio||Provides good return path for every I/O to reduce loop inductance and noise|
|Slow Slew Rate||Reduces rise/fall times of the output driver to reduce simultaneous switching (SSN) noise|
|Staggered Output Delay Control||Spaces out simultaneous switching outputs (SSO) switching time to reduce SSN noise|
|On-chip Termination||Controls on-chip termination for proper line termination and impedance matching, which helps prevent reflections on the transmission line. Eliminates the need for external termination resistors to lower system cost and simplify PCB deign|
|On-Die Decoupling||Provides high-frequency decoupling and suppresses power noise. Reduces the number of external PCB decoupling capacitors to lower system cost and simplify PCB design|
|Table 3. High-Speed Differential Signaling|
|LVDS Buffer Enhancement||Includes programmable pre-emphasis and programmable VOD features to compensate for signal attenuation|
|Dynamic Phase Alignment (DPA)||Compensates for skew in board layout, allowing source-synchronous I/O to operate at higher data rates, which increases the likelihood of successful PCB layout|
|Soft-CDR||Soft-CDR circuitry at the receiver allows implementation of asynchronous serial interfaces with embedded clock at data rates up to 1 Gbps|
- Signal Integrity Center
- Simulation Models: HSPICE, IBIS
- Power Distribution Network (PDN) graphical design tool