Cyclone® IV FPGAs help you meet signal integrity requirements by providing transceivers with best-in-class jitter characteristics. Leveraging Altera's long-standing technical expertise in transceiver technology, Cyclone IV GX FPGAs also include advanced transceiver features. The device features simplify PCB design and compensate for inevitable board losses through multi-tap pre-emphasis, programmable VOD, and on-chip termination (see Table 1). Additional features enhance the Cyclone IV FPGA die and package, resulting in excellent signal and power integrity and maximum user flexibility (see Table 2).
Pre-emphasis, equalization, and VOD are all dynamically programmable in Cyclone IV GX FPGAs. This allows you to change levels while the transceiver is operating, making it simpler to tune the interface for interoperability testing or to change a setting, depending on a board's location in a system. Table 2 shows the I/O and packaging technology features in Cyclone IV FPGAs.
| Table 2. Cyclone IV (GX and E) I/O and Packaging Features for Optimal Signal Integrity | |
| Features | Benefits |
|---|---|
| 12:1:1 User I/O, Ground, and Power Ratio | Provides low impedance return path for every I/O connection to reduce loop inductance and noise. |
| Adjustable Slew Rate Control | Controls signal edge rate to reduce noise. |
| On-Chip Termination | Eliminates the need for external termination resistors to lower system cost and simplify PCB design. |
| On-Package and On-Die Decoupling | Provides high-frequency decoupling and suppresses power noise. Reduces the number of external PCB decoupling capacitors to lower system cost and simplify PCB design. |
12:1:1 User I/O, Ground, and Power Ratio
Cyclone IV package designs reduce noise while providing the optimum number of user I/O pins. Cyclone IV pin-outs provide a low-impedance return path for every single I/O pin and, therefore, reduce VCC sag and ground bounce.
Adjustable Slew Rate Control
Cyclone IV FPGAs offer adjustable slew rate control, allowing you to change the signal edge rate for better signal integrity. You can use three different settings to match the desired I/O standard and control noise and overshoot. This flexibility allows you to have better control over the design to achieve optimum system performance and excellent signal integrity.
On-Chip Termination
Cyclone IV FPGAs offer series on-chip termination (OCT) technology on all I/O pins to further improve signal integrity performance and eliminate the need for external termination resistors. This technology lowers system cost and simplifies PCB design.
On-Die Decoupling
On-die decoupling capacitors provide high-frequency decoupling that external PCB decoupling capacitors and voltage regulator modules cannot support. These low-inductance capacitors suppress power noise for excellent signal integrity performance.
The decoupling capacitors also reduce the number of external PCB decoupling capacitors, saving precious board space, reducing cost, and greatly simplifying PCB design.
This page contains links to Cyclone IV FPGA resources that will help you develop, lay out, and verify your high-speed design.
IBIS and SPICE Models
Correlated Cyclone IV I/O SPICE and IBIS models will be available shortly.
NDA required; contact your local Altera® sales representative for details.
Documentation
- Power Delivery Network (PDN) Tool User Guide (PDF)
- Device-Specific Power Delivery Network (PDN) Tool User Guide (PDF)
- Cyclone IV Device I/O Features (PDF)
- High-Speed Serial Interfaces in Cyclone IV GX Devices (PDF)
- External Memory Interfaces in Cyclone IV Devices (PDF)
- Guidelines for Designing High-Speed FPGA PCBs (PDF)
- Basic Principles of Signal Integrity (PDF)
