Cyclone® III 65-nm FPGAs offer best-in-class signal integrity to reduce the risk of system failures, simplify the design process, and enhance design performance and flexibility. Table 1 shows the Cyclone III enhancements for signal integrity.
Signal Integrity
| Table 1. Cyclone III FPGA Enhancements for Signal Integrity | |
| Enhancement | Benefit |
|---|---|
| 12:1:1 User I/O, Ground, and Power Ratio | Provides low impedance return path for every I/O to reduce loop inductance and noise. |
| Adjustable Slew Rate Control | Controls signal edge rate to reduce noise. |
| On-Chip Termination | Eliminates the need for external termination resistors to lower system cost and simplify printed circuit board (PCB) design. |
| On-Die Decoupling | Provides high-frequency decoupling and suppresses power noise. Reduces the number of external PCB decoupling capacitors to lower system cost and simplify PCB design. |
12:1:1 User I/O, Ground, and Power Ratio
The Cyclone III package designs reduce noise while providing the optimum number of user I/O pins. Cyclone III pin-outs provide low impedance return path for every single I/O and, therefore, reduce VCC sag and ground bounce.
Adjustable Slew Rate Control
Cyclone III FPGAs offer adjustable slew rate control, allowing you to change the signal edge rate for better signal integrity. You can use three different settings to match the desired I/O standard and control noise and overshoot. This flexibility allows you to have better control over the design to achieve optimum system performance and excellent signal integrity.
On-Chip Termination
Cyclone III FPGAs offer series on-chip termination (OCT) technology on all I/O pins to further improve signal integrity performance and eliminate the need for external termination resistors. This technology lowers system cost and simplifies PCB design.
On-Die Decoupling
On-die decoupling capacitors provide high-frequency decoupling that external PCB decoupling capacitors and voltage regulator modules cannot support. These low-inductance capacitors suppress power noise for excellent signal integrity performance.
These decoupling capacitors also reduce the number of external PCB decoupling capacitors, saving precious board space, reducing cost, and greatly simplifying PCB design.
This page contains links to Cyclone III FPGA resources that will help you develop, layout, and verify your high-speed design.
IBIS and SPICE Models
Correlated Cyclone III I/O SPICE and IBIS models will be available shortly.
- IBIS Models
- SPICE Models
- NDA required; contact your local Altera® sales representative for details
Documentation
- Cyclone III Device I/O Features (PDF)
- High-Speed Differential Interfaces in Cyclone III Devices (PDF)
- External Memory Interfaces in Cyclone III Devices (PDF)
- Package Information for Cyclone III Devices (PDF)
- Guidelines for Designing High-Speed FPGA PCBs (PDF)
- Basic Principles of Signal Integrity (PDF)
