Altera performed extensive validation of device and system-level external memory interfaces. Lab experiments were carried out to quantify signal integrity metrics such as SSN, eye-opening, data-valid window, edge rates, and jitter. The following provides details on the experiment setup for the Stratix® II SSTL-18 Class II eye diagram testing at 533 Mbps (see Figure 1).
Figure 1. Stratix II SSTL-18 Class II 64-Channel Eye Diagram Experiment Setup
An input clock frequency of 266.5 MHz clocks the phase-locked loop (PLL), which in turn clocks the pseudo-random binary sequence (PRBS) generator and the 64 double data rate (DDR) registers. The PRBS generator generates random sequences of data for the eye diagram, while each DDR register increases the data rate for each of the 64 channels by 2 times to 533 Mbps.
SSTL-18 Class II terminations with loading capacitors mimic a real DDR2 system memory bus with DIMM as the load. The eye diagram is captured at the receiving end of the bus using a high impedance active probe and a digital oscilloscope.
- Tektronix TDS7404B 4 GHz digital phosphor oscilloscope
- Tektronix P720 4 GHz high impedance active probe
- Agilent 81130A pulse generator
- Power supplies
- Check out the Stratix II FPGA's DDR2 eye diagram
- Check out the Stratix II FPGA's LVDS eye diagram
- Check out the Stratix II vs. Virtex-4 FPGA eye diagram comparison