Stratix® II GX transceivers provide highly configurable pre-emphasis and equalization circuitry to compensate for transmission line losses and allow successful transmission at up to 6.375 Gbps. However, every channel is different, which leads to unique settings on each link. The only accurate way to determine the optimum settings is to either perform an HSPICE simulation or to use Altera’s Signal Integrity Kit, but this can be extremely time-consuming because a large number of different settings must be assessed, with simulation cycle times measured in hours.
Finding the best settings to equalize system components requires multiple iterations until the best eye diagram is found. Altera's pre-emphasis and equalization link estimator (PELE) technology can take weeks off a standard simulation process and greatly improve simulation accuracy. It uses correlated models developed specifically for Altera’s transceivers, along with user-defined output drive voltage settings and scattering parameters (S-parameters) in Touchstone format. The S-parameters are taken from either a PCB layout or from bench measurements to calculate the optimum pre-emphasis and equalization settings.
Once these settings are computed using proprietary algorithms, the PELE information is massaged by the EDA tool platform, such as Mentor Graphics' Stratix II GX Design Kit for HyperLynx. The EDA tool creates an include file that is ready for use in an HSPICE, or ELDO, simulation.
Figure 1. Typical Line Block Diagram Taken from HyperLynx
This analog simulation verifies channel operation and is correlated to actual silicon performance, thus reducing the number of simulation cycles required, or used, to optimize pre-emphasis and equalization settings for the actual device on a board.
Board S-parameters can be:
- Extracted directly from the PCB layout using EDA tools
- Extracted from an existing board using time domain reflectometry (TDR) and time domain transmissivity (TDT) and then these measurements can be post-processed using IConnect software from Tektronix
- Extracted from an existing board using a Vector Network Analyzer (PDF)
As shown in Figure 2, PELE, along with the EDA tools suite in which it is embedded, can be used both for new board design simulations and to predict the capabilities of the transceiver in legacy systems and backplanes.
Figure 2. Stratix II GX Eye Diagram Simulation from HyperLynx
Contact your local Altera® sales office for additional information and details on the EDA platforms that currently support PELE technology.
