Stratix II GX Signal Integrity Center

This page contains links to Stratix^® II GX FPGA design resources that help you develop, optimize, and verify your high-speed channel and board design and signal integrity.

• Plug & Play Signal Integrity with the industry’s first adaptive equalizer – Altera’s ADCE
• Transceiver dynamic reconfiguration to support multiple protocols, data rates and physical medium attachment (PMA) settings
• Reduce risk, development time, and cost with the new Stratix II GX high-speed board design advisor documents
• Evaluate the simultaneous switching noise in your design with the Stratix II GX early SSN estimator
• Learn how pre-emphasis and equalization link estimator (PELE) technology can take weeks off your Stratix II GX channel simulation
• Perform online characterization with the Stratix II GX eye diagram viewer

• Stratix II GX Device Handbook
  • Stratix II GX Transceiver Architecture Overview (PDF)
  • Selectable I/O Standards in Stratix II & Stratix II GX Devices (PDF)
  • High-Speed Source-Synchronous Differential I/O Interfaces in Stratix II GX Devices (PDF)
  • Package Information for Stratix II & Stratix II GX Devices (PDF)
  • High-Speed Board Layout Guidelines (PDF) 
• Application notes
  • Guidelines for Designing High-Speed FPGA PCBs (PDF)
  • Stratix II GX SSN Design Guidelines (PDF)
• White papers
  • Basic Principles of Signal Integrity (PDF)
• Conference papers
  • Digitally Assisted Adaptive Equalizer in 90 nm With Wide Range Support From 2.5 Gbps-6.5 Gbps (PDF) (Presented at DesignCon 2007)
  • Equalization Challenges for 6-Gbps Transceivers Addressed by PELE—A Software-Focused Solution (PDF) (Presented at DesignCon 2007)
  • FPGA Design for Signal and Power Integrity (PDF) (Presented at DesignCon 2007)
  • Pre-Emphasis and Equalization Parameter Optimization With Fast, Worst-Case/Multibillion-Bit Verification (PDF) (Presented at DesignCon 2007)
  • Calibration Techniques for High-Bandwidth Source-Synchronous Interfaces (PDF) (Presented at DesignCon 2007)

Device Models

• IBIS Models
• SPICE Models
• Transceiver ELDO Model
• Silicon Design-In Kit for Mentor Graphics^® HyperLynx Platform
• Silicon Design-In Kit for Cadence Allegro Platform

Simulation Tools and Technology

• PELE Technology

Design-in kits for the Cadence Allegro platform and the Mentor Graphics ICX and HyperLynx tools contain validated models, topology files, layout constraints, example PCB files and footprints, tutorials, documentation, scripts, and other utilities. The design-in kits simplify and speed system modeling and PCB design.

• Transceiver Signal Integrity Development Kit, Stratix II GX Edition
  • Targeted at evaluating transceiver signal integrity and features
  • Shipped with easy to use configuration tools to simplify analysis