Stratix III Device Signal and Power Integrity
Stratix® III 65-nm FPGAs offer best-in-class signal integrity to reduce the risk of system failures, simplify the design process, and enhance design performance and flexibility. Detailed analysis and effort have been put into enhancing the Stratix III FPGA die and package, resulting in excellent signal and power integrity. Table 1 shows the Stratix III enhancements for signal integrity.
| Table 1. Stratix III FPGA Enhancement for Signal Integrity |
| Enhancement |
Benefit |
| 8:1:1 User I/O, Ground, and Power Ratio |
Provides low impedance return path for every I/O to reduce loop inductance and noise. |
| Optimized Die- and Package-Level Signal Return Path |
Optimizes return path with low impedance to reduce loop inductance and noise. |
| Adjustable Slew Rate Control |
Controls signal edge rate to reduce noise. |
| Staggered Output Delay Control |
Spaces out simultaneous switching outputs (SSO) switching time to reduce simultaneous switching noise (SSN). |
| Dynamic On-Chip Termination |
Dynamically controls on-chip termination for proper line termination and impedance matching, which helps to prevent reflections on the transmission line. Eliminates the need for external termination resistors to lower system cost and simplify printed circuit board (PCB) design. |
| On-Package and On-Die Decoupling |
Provides high-frequency decoupling and suppresses power noise. Reduces the number of external PCB decoupling capacitors to lower system cost and simplify PCB design. |
| LVDS Buffer Enhancement |
Includes programmable pre-emphasis and programmable Voltage Output Differential (VOD) features to compensate for signal attenuation. |
8:1:1 User I/O, Ground, and Power Ratio
This new Stratix III FPGA package design (see Figure 1) reduces noise while providing the optimum number of user I/O pins. The new package pin-out pattern provides low impedance return path for every single I/O and therefore, reduces VCC sag and ground bounce.
Figure 1. Stratix III Package Pin-Out
Optimized Die- and Package-Level Signal Return Path
In addition to having a new package pin-out, Stratix III FPGAs also received die- and package-level enhancements. Extensive distributed ground bumps on the Stratix III FPGA die enhance the signal return path and lower crosstalk between I/O pins.
- All traces are referenced to solid, continuous planes with more layers
- More ground reference vias within the package
- Better distribution of power/ground balls
- More vias from package balls to planes
- Overall better return paths and better PDN design
Adjustable Slew Rate Control
Stratix III FPGAs offer adjustable slew rate control, allowing you to change the signal edge rate for better signal integrity. You can use four different settings to match the desired I/O standard and control noise and overshoot. This flexibility allows you to have better control over the design to achieve optimum system performance and excellent signal integrity.
Staggered Output Delay Control
The staggered output delay control feature lowers SSN while providing maximum performance. This feature reduces the number of signals switching at the same time by delaying some SSO edges, which spaces out the output switching time and reduces SSN. Additionally, this feature also allows you to adjust signal duty cycle and skew compensation due to board trace mismatch. The flexibility introduced by this feature simplifies system and PCB design.
Dynamic On-Chip Termination
Stratix III FPGAs offer advanced dynamic on-chip termination (OCT) technology on all I/O pins to further improve signal integrity performance and eliminate the need for external termination resistors. This technology lowers system cost and simplifies PCB design.
The new dynamic OCT feature for single-ended termination enables terminations to be changed dynamically, which is extremely useful for bidirectional interfaces (e.g., interfacing with DDR memories where the OCT schemes on Stratix III FPGAs can be changed depending on the read or write cycle). Stratix III FPGAs also provide on-chip differential termination for high-speed interfaces.
Built-in enhanced digital automatic calibration circuitry on all Stratix III FPGA I/O pins provide precise impedance control and compensate impedance change due to temperature and voltage fluctuation, providing repeatable and predictable termination.
On-Package and On-Die Decoupling
Embedded on-package and on-die decoupling capacitors provide high-frequency decoupling that external PCB decoupling capacitors and voltage regulator modules cannot support. These low-inductance capacitors suppress power noise for excellent signal integrity performance.
These decoupling capacitors also reduce the number of external PCB decoupling capacitors, saving precious board space, reducing cost, and greatly simplifying PCB design.
LVDS Buffer Enhancement
The new enhanced Stratix III FPGA LVDS I/O buffers provide programmable pre-emphasis and programmable VOD features to address high-speed signal requirements for long- and short-trace lengths and reduced signal attenuation.
The programmable pre-emphasis compensates high-frequency attenuation by boosting up high-frequency signal components. Four different settings allow adjustment and compensation for various trace lengths, transmission line characteristics, and power, enabling you to optimize the level of pre-emphasis for each scenario. See Figures 2 and 3.
Figure 2. Example of Signal Without Pre-Emphasis Across a 40-Inch Backplane
Figure 3. Example of Signal With Pre-Emphasis Across a 40-Inch Backplane
The programmable VOD settings enable you to adjust output eye height to optimize for trace length and power consumption. A higher VOD swing improves voltage margins at the receiver end while a smaller VOD swing reduces power consumption.
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