The Basics of Signal Integrity, Part II
Part I
Part II
Signal Attenuation
High-frequency signals are subject to losses along transmission lines, which interfere with the receiver’s ability to interpret the information. Table 1 lists some causes of the losses due to the transmission medium used to carry the signal.
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Table 1. Causes of Losses Along Transmission Lines
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Cause
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Description
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Dielectric Absorption
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High-frequency signals excite molecules in the insulator causing it to absorb signal energy. This results in a reduction of the signal strength. Dielectric absorption is related to the printed circuit board (PCB) material being used, and can be improved by careful selection of material.
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Skin Effect
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Varying current waveforms, caused by AC and high-frequency signals, tend to travel on the surface of a conductor. This results in the self-inductance of the material producing an increased inductive reactance at high frequencies, forcing electrons to the surface of the material. The effective reduction of conductive area causes an increase of resistance and therefore attenuation of the signal. Increasing track width can reduce skin effect, but this is not always possible. Figure 3 illustrates this problem.
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Careful selection of insulating material and track layout can help to overcome the issues of attenuation. Table 2 lists the circuitry in Stratix® GX Transceiver FPGAs that overcomes attenuation problems.
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Table 2. Circuitry in Stratix GX Transceiver FPGAs to Overcome Attenuation Problems
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Cause
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Description
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Pre-Emphasis
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High-frequency attenuation cannot be achieved by boosting the signal strength alone, as this will also amplify noise and jitter associated with the signal. Pre-emphasis boosts only the high frequency components of the signal by increasing the level of the first transmitted symbol, while leaving the next symbols untouched—if they were transmitted at the same level.
For example, if a signal were to transmit a high level for three symbols, only the first symbol would be boosted, while the next two would be transmitted at the usual level. (See figure 3.) If a single symbol were transmitted at a high level, this would also be boosted.
Pre-emphasis is also a key function to overcome the effects of pattern-dependant jitter, including loss of amplitude, displacement in time, and rounded signal edges.
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Receiver Equalization
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Dedicated receiver circuitry is used to attenuate the high frequency components of the signal as it arrives at the receiver to compensate for line losses. Stratix GX devices have programmable equalization for 20” and 40” transmission lines.
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Figure 3. Pre-Emphasis Over Two Unit Intervals
Cross-Talk
Whenever a signal is driven along a wire, a magnetic field is developed around that wire. If two wires are placed adjacent to each other, it is possible that the two magnetic fields will interact with the each other, causing a cross-coupling of energy between signals, known as cross-talk. Table 3 illustrates the types of coupling that exist which predominantly cause cross-talk.
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Table 3. Types of Coupling That Cause Cross-Talk
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Coupling
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Description
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Mutual Inductance
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This is the effect of induced current from a driven wire, or aggressor, appearing on the quiet wire, or victim, by means of a magnetic field. Mutual inductance causes positive waves to appear on the near end of the victim line (closest to the transmitter) causing near-end inductance, while negative waves appear at the far end of the transmission line (nearer to the receiver), causing far-end cross-talk.
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Mutual Capacitance
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This is the coupling of two electric fields, where electrical current proportional to the rate of change of voltage in the driver is injected into the victim line. Mutual capacitance causes positive waves to appear at both ends of the transmission line.
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Cross-talk can be significantly reduced by careful PCB design. The following steps describe how to reduce cross-talk in either micro-strip or strip-line layouts:
- Widen spacing between signal lines as much as routing restrictions will allow
- Design the transmission line so the conductor is as close to the ground plane as possible; this will couple the transmission line tightly to the ground plane and help decouple it from adjacent signals
- Use differential routing techniques wherever possible, especially for critical PCB traces
- Route signals on different layers, orthogonal to each other if there is significant coupling
- Minimize parallel run lengths between signals; route with short parallel sections and minimize long coupled sections between nets
Simultaneous Switching Outputs
As digital circuitry increases in speed, output-switching times decrease. Faster switching times cause higher transient currents within the outputs as the load capacitors discharge. If a number of outputs were to switch simultaneously from logic-high to logic-low, the charge will be stored in the I/O load capacitances to flow into the device. This sudden flow of current exits the device through internal inductances onto the board ground, causing a voltage to develop. This results in a voltage difference between the device and the board ground, momentarily developing a low voltage signal on the I/O above the ground level. This is known as "ground bounce". The bounce effect can cause an output-low to be seen as a high by other devices on the board.
Ground bounce can be reduced by following a number of board based design rules as outlined in AN 315: Guidelines for Designing High-Speed FPGA PCBs (PDF).
Altera® high-speed solutions provide pin slew rate control, which allows the designer to slow down the driver and therefore reduce the bounce effect. Additionally, the devices include multiple power and ground pins, thereby allowing the designer to locate a high-speed I/O pin close to a ground pin to reduce the effects of simultaneous switching outputs (SSO).
The challenges of high-speed design require some additional effort to ensure signal integrity. This can be achieved by following some simple analogue design rules and by using careful PCB layout techniques. Altera high-speed programmable logic devices provide many features to help support high-speed design, programmable slew rate control, and on-chip termination technology help to make designers’ work easier.
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