From a distance, basing a system design on an FPGA can appear daunting. The sheer flexibility of the FPGA, from the choice of CPUs to the ability to create accelerators from RTL to the range of power-management options, would appear to turn a system design into an IC design project.
But the majority of the time, reality is nothing like that appearance. Most FPGA-based system designs employ a reference design, or build up from an application development kit, or leverage extensive intellectual property (IP) libraries to do the heavy lifting of detailed FPGA design. In most cases the system design team can treat the FPGA as a customizable application-specific standard product or even as an advanced microcontroller, and put their energy into features that will differentiate their system, not into reinventing the wheel.
In some cases the system design team may concentrate on adding only finishing touches and differentiating features, because a full system-level reference design already exists for their application. Or they may focus on implementing the board-level system because an FPGA reference design exists that already meets the system requirements. In other cases the reference design will provide a core function, around which the design team may assemble IP to complete the system-level IC design. In general the reference design serves two purposes—to provide a working example of how to implement the functions required in a particular application, and to encapsulate the most critical blocks of the design in completed modules so the design team doesn’t have to optimize them. For a list of reference designs for Altera® FPGAs, see the All Reference Designs page.
Figure 1. 4K Video Format Conversion Reference Design Block Diagram
Like reference designs, development kits inhabit a broad spectrum, from kits intended simply to ease evaluation of a particular FPGA chip to kits that attach specific peripherals and include the kernel functions for a particular application. The kits are all intended to get a design team part-way along the road to a finished system. Using this head start, the system designers can focus on the functions that will differentiate their product, rather than on building and debugging prototypes or redeveloping commonly-used functions from scratch. For a list of Altera's development kits, see the All Development Kits page.
Even in cases where no reference design or development kit exists, it is still possible for the system design team to save significant effort by adopting IP cores to implement large and demanding functions. In many cases, critical functions such as digital signal processing (DSP) units or protocol controllers have already been implemented as configurable hard IP cores on the FPGA. At a minimum, soft IP cores allow designers to drop the code for a block into their design knowing that the block has already been verified—and often, that it has already been used in other systems. For a list of Altera's IP cores, see the All Intellectual Property page.
But in some cases it is possible to go further. As IP developers have filled out their libraries to include CPUs, system interconnect, interface controllers, signal-processing and encryption functions, and control algorithms, it has become possible to construct whole systems by gluing together existing IP blocks. And when the IP has been written to conform to some simple layout, pin definition, and timing conventions, it becomes possible to create a tool, such as Altera’s Qsys system integration tool, that automates most of the process of assembling IP into a system. Such a process can approach the efficiency of using a full reference design.
Another significant example is in construction of signal-processing systems. It is possible now to move directly, with automation support, from MathWorks development of algorithms to FPGA implementation using an Altera tool called DSP Builder. For more information about Altera's DSP solutions portfolio, see the Accelerating DSP Designs with the Total 28-nm DSP Portfolio (PDF) white paper.
Nor should we overlook the importance of verification IP, especially for functions defined by standards. No experienced system designer needs to be reminded of the growing schedule and resource impacts of verification. One special point for FPGA-based systems is the ability to create hardware transaction generators and checkers, and thus to perform transaction-based verification at wire speed, and to use the FPGA as an instrumentation package to debug the rest of the system. For high-speed serial interfaces in particular, Altera has created built-in hardware to measure eye openings and bit error rates, allowing effective system interconnect troubleshooting without external test equipment.
Finally, we should observe that the breadth of an FPGA family can itself boost design efficiency. Placement and timing closure become exponentially more difficult as the design requirements approach the physical capacity and speed limits of the chip. Being able to simply move to a larger device or a faster speed grade can dramatically reduce design effort.
For most system design teams, creating a new system-level IC is simply not on their agenda. Fortunately, neither is detailed chip design necessary in order to employ an FPGA as the heart of the system. Reference designs that can provide up to fully-functional board-level systems, development kits that give design teams advanced jumping-off points in specific application areas, formidable libraries of IP, and tools that assemble IP into working subsystems can all speed a system design effort on its way and prevent it from devolving into a detailed chip design project.