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Design Planning Guidelines for High-Density FPGAs
(ODSW1130)
1 Hour
Online Course
Course Description
Designs are often partitioned into multiple blocks with multiple designers. The flexibility of advanced FPGAs means the pin layout, power consumption, & timing for each design block are dependent on the final design implementation. System architects must resolve these issues during the integration phase, often leading to problems that affect time to market & cost. Potential problems can be solved earlier in design cycle with proper planning. You will learn how the Quartus® II software v. 8.0 can help with:
- Device Selection & Device Migration Planning
- Programming/Configuration Method Selection
- Early Pin Planning & I/O Analysis
- Early Power Estimation
- Planning Debug Options
- Planning for Incremental Compilation
- Early TIming Estimation
At Course Completion
- Identify reasons why you should perform various planning tasks early in the design process
- Identify how Quartus II features can help improve your design productivity
- Use a checklist of things to consider during the early design process
Prerequisites
We recommend completing the following courses:
Skills Required
- Background in digital logic design
- An understanding of basic FPGA design flow
- One of the following:
- Completion of the "Using the Quartus II Software: An Introduction" online training course
- Completion of the tutorial available in the Quartus II software online help
- A solid working knowledge of the Quartus II software
Applicable Training Curriculum
This course is part of the following Altera training curriculum:
Class Schedule
Request a class in your region
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