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Using High Performance Memory Interfaces in Altera FPGAs
(OMEM1110)
1.5 Hours
Online Course
Course Description
Memory interface design for FPGAs has traditionally been a complex process. This training will highlight the ease with which high performance memory controllers can be implemented and tested in an Altera FPGA using the Quartus® II software v. 7.1. You can select, parameterize, and test your memory controller IP easily by following the guidelines discussed herein. We will focus on “High Performance” DDR-style memory interfaces – i.e. those that utilize Altera’s new ALTMEMPHY self calibrating PHY block. This auto-PHY block can be used within our own IP or combined with your own custom controller.
At Course Completion
- How to find and parameterize high performance Altera® memory controller IP
- How to instantiate and test high performance memory controller IP in your design
- Setting up the RTL simulation in ModelSim® software (from within Quartus II software)
- Launching static timing analysis with TimeQuest
- How to correct some common timing problems
- What the ALTMEMPHY auto-calibrated, dynamic PHY brings you
Prerequisites
We recommend completing the following courses:
Skills Required
- Background in digital logic design
- Basic knowledge of memory interfaces
- Familiarity with the Quartus II FPGA design software
- Prior exposure to the TimeQuest timing analysis tool
Applicable Training Curriculum
This course is part of the following Altera training curriculum:
Class Schedule
Request a class in your region
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