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Using the Quartus II Software: Managing Design Changes with Chip Editor
(ODSW1152)
1 Hour
Online Course
Course Description
In this course you will learn how to use Chip Editor in the Quartus® II software v. 4.0 to analyze and modify post place-and-route FPGA designs. You will learn how the Chip Editor can be used to examine the configuration of FPGA design resources such as logic elements, phase locked loops (PLLs), and input/output (I/O) elements used by your design. You will see how you can enable/disable or change parameters of the features associated with these design resources as well as keep track of all the design changes right from the Quartus II software interface. You will also see practical examples of using Chip Editor for correcting minor design bugs and optimizing timing without having to recompile the entire design and therefore to shorten the design turn-around time.
At Course Completion
- Viewing FPGA structures using Chip Editor
- Editing FPGA atom properties to facilitate design changes
Prerequisites
We recommend completing the following courses:
Skills Required
- Background in FPGA or ASIC design
- Knowledge of FPGA internal structures
- Knowledge of basic Quartus II software functionality
Applicable Training Curriculum
This course is part of the following Altera training curriculum:
Class Schedule
Request a class in your region
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