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Chinese Version: Using the Quartus II Software: Simulation
(OCDSW1175)
0.5 Hours
Online Course
Course Description
This course has Simplified Chinese audio. You will learn how to use the simulator found in the Quartus® II software v. 6.0 to perform functional and timing simulation. You will learn how to create a vector waveform file for use as the simulator stimulus. You will also learn how to take advantage of various features of the simulator including breakpoints, power-analysis file generation and waveform file to HDL conversions.
At Course Completion
- Simulating an FPGA or CPLD design in the Quartus II software
- Creating a vector waveform file
- Adding breakpoints to pause simulation or generate messages
- Viewing and comparing simulation results
Prerequisites
We recommend completing the following courses:
Skills Required
- Background in digital logic design
- Familiarity with the FPGA or CPLD design flow
- Knowledge of schematic, VHDL or Verilog HDL design entry
Class Schedule
Request a class in your region
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