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Chinese Version: Design Debugging Using the SignalTap II Logic Analyzer
(OCDSW1165)
1 Hour
Online Course
Course Description
This course has Simplified Chinese audio. This training will present the benefits the SignalTap® II logic analyzer provides for on-chip debugging using the Quartus® II software v. 6.0. Upon completion of this training, you will be able to recognize and know how to perform the major tasks required for a SignalTap II debugging process flow. You will also know where to go to find additional support and information resources.
At Course Completion
Given an FPGA design, you will be able to:
- Add one or more instances of the SignalTap II logic analyzer to a design.
- Configure the SignalTap II logic analyzer to debug the design.
- Define Power-Up and Run-Time trigger events.
- Use incremental compilation to reduce recompile times.
- Operate the SignalTap II logic analyzer to capture data as defined by the trigger settings.
- Analyze data captured by the trigger event(s) and use it to locate and fix bugs in the design.
Prerequisites
We recommend completing the following courses:
Skills Required
- Basic knowledge of the Quartus II software including incremental compilation, the Nios® II processor and the Nios II IDE
- Knowledge of external logic analyzer operations (optional)
Applicable Training Curriculum
This course is part of the following Altera training curriculum:
Class Schedule
Request a class in your region
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