Latest Member of the Stratix IV FPGA Series is the Industry's Highest Density FPGA, Offering Highest Performance and Lowest Power in Its Class
San Jose, Calif., September 14, 2009—Altera Corporation (NASDAQ: ALTR) today announced it increased the high-end density range of its 40-nm Stratix® IV E FPGAs to an industry-leading 820K logic elements (LEs). The Stratix IV EP4SE820 FPGA is the industry's highest density, highest performance and lowest power FPGA in its class. The EP4SE820 FPGA is ideally suited for a variety of high-end digital applications that require resource-rich FPGAs, including ASIC prototyping and emulation, wireline, wireless, military, and computer and storage applications.
Altera's Stratix IV E FPGAs feature four devices ranging in density from 230K to 820K LEs. The new EP4SE820 delivers 53 percent higher density than Altera's EP4SE530 device and is at least one speed grade faster than the closest competitor's largest offering. The density, performance and power-saving features in the EP4SE820 FPGA enable customers to simplify their design partitioning, accelerate their verification cycle, and reduce their total system power.
Increasing the number of LEs in Stratix IV E FPGAs to 820K gives ASIC-prototyping designers the ability to implement much larger ASIC designs on a single FPGA, which simplifies board design and minimizes the number of design partitions. For designers wanting to move their design into an ASIC after FPGA prototyping, Altera offers a low-risk, low-cost migration path to ASIC production with its HardCopy
Key Features of the Stratix IV EP4SE820 FPGA
- 820K LEs and 650K registers
- 23.1 Mbits of 600-MHz embedded memory
- 960 18x18 multipliers running up to 550 MHz
- 1,120 I/Os
- 1.25-Gbps LVDS performance
- Altera's patented Programmable Power Technology
Altera's high-end Stratix FPGAs allow for seamless migration between families so customers can get started on their Stratix IV E FPGA designs today. This migration capability also allows users to move their existing Stratix III FPGA designs to Stratix IV E FPGAs without having to change the device pin-outs or the circuit board layout.
Compile-Time Advantage Using Quartus II Software
One of the most critical issues that designers of high-density FPGAs face is minimizing compile times so they can bring products to market faster. Altera® Quartus® II design software offers several productivity features to Stratix IV FPGA users that enable faster overall timing closure. Features such as advanced place-and-route algorithms, multiprocessor support and incremental compile reduce customers' compile times two to three times on average when compared to the nearest competitor's 40-nm high-density FPGAs.
“Customers, particularly in the ASIC prototyping and emulation space, demand bigger and faster FPGAs, and we are meeting their demand by offering the industry's largest FPGA,” said Luanne Schirrmeister, senior director of component product marketing at Altera. “The resource-rich EP4SE820 FPGA enables customers to fit more logic into their FPGA so they can deliver greater product differentiation at a lower cost.”
Altera is currently shipping engineering samples of selected members of its Stratix IV E FPGAs. For additional information about Altera's Stratix IV E FPGAs, including pricing, or to start designing your EP4SE820-based design, contact your local Altera sales representative. For general information regarding Altera's Stratix IV FPGAs, visit www.altera.com/pr/stratixiv/20090914.
Altera programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. Find out more about Altera's FPGA, CPLD and ASIC devices at www.altera.com. To subscribe to Altera's RSS/XML news feeds, visit Altera RSS Feeds.