San Jose, Calif., June 22, 2010—Expanding its FPGA solutions for the surveillance market, Altera Corporation (NASDAQ: ALTR) announced today the industry's first high-definition (HD), surveillance internet protocol (IP) camera reference design on a single FPGA. This unique solution features Altera's low-cost Cyclone® III or Cyclone IV FPGAs and intellectual property from Eyelytics and Apical supporting AltaSens' 1080p60 A3372E3-4T and Aptina's 720p60 MT9M033 HD Wide Dynamic Range (WDR) CMOS image sensors. The all-in-one solution offers surveillance equipment manufacturers the ability to reduce board space, lower power consumption, increase flexibility and reduce development time compared to previous architectures using traditional digital signal processors and ASSPs.
Traditional digital signal processors and ASSPs don't have the processing power required to accept the large bandwidth of data from 1080p and 720p WDR CMOS sensors (for instance, a full HD raster is 2200x1125 pixels x 16+ bits per pixel x 60 frames per second, resulting in >2 Gbps bandwidth). Altera's Cyclone series FPGAs deliver the bandwidth and processing performance needed, handling large amounts of data generated by today's HD WDR CMOS image sensors. In previous designs, HD WDR camera systems required FPGAs to perform the “front end” data processing while a digital signal processor or an ASSP handled the “back end” video encoding. Now, all of these chips can be replaced by a single Altera® FPGA.
The functions of Altera's HD surveillance IP camera reference design include:
- Apical's ISP incorporating best-in-class WDR processing “iridix” together with advanced temporal and spatial noise reduction
- Apical's “checkerboard demosaic” core for the Altasens A3372E3-4T WDR mode
- “3A” functions, such as auto exposure and auto white balance implemented in software on Altera's Nios® II embedded soft core processor
- Eyelytics' H.264 video encoder, capable of 720-line progressive 30 frames-per-second encoding or 1080-line progressive 15 frames-per-second encoding in main profile
- Altera's triple-speed Ethernet MAC intellectual property core
By eliminating the need for digital signal processors or ASSPs and combining all of these functions into one Altera FPGA, designers can take advantage of the cost and power savings with reduced board space. Altera's single-chip solution reduces power consumption by more than 50 percent compared to previous designs.
The bundling of a comprehensive list of intellectual property in this reference design gives designers a head start in camera development, shortening development time by as much as one year. All camera designers have to do is customize the FPGA with their own specific features, such as adding their own software for motion detection, and pan, tilt and zoom control.
“Much like the video display industry, our surveillance customers expect high-quality video images,” said Michael Samuelian, director of the industrial and automotive business unit at Altera. “Altera is taking surveillance another step further by delivering a complete single-chip solution that not only addresses the trends from standard definition to high definition, standard CMOS sensors to WDR CMOS sensors, but makes it more cost effective for surveillance-camera designers to produce high-resolution images over an internet protocol network.”
To learn more about Altera's single-chip HD IP camera reference design that's available now, visit www.altera.com/pr/surveillance2.
Altera programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. Find out more about Altera's FPGA, CPLD and ASIC devices at www.altera.com. Follow Altera via Facebook, RSS and Twitter.