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Intellectual Property (IP) Digital Signal Processing / AI Artificial Intelligence Error Correction Filters /Transforms Floating Point Modulation Video and Image Processing Interfaces Audio / Video Communication Compute Express Link (CXL) Ethernet High Speed Networking / Security PCI Express (IP) Serial Memory Controllers DMA Flash SDRAM SRAM Soft Embedded Processors RISC V Transceivers & Basic Functions Clocks, PLLs and Resets Simulation, Debug and Verification Transceivers
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100 Gbit/s IEEE 802.3bj RS Encoder/ Decoder

The Creonic IP cores are the ideal solution for throughputs beyond 10 Gbit/s for FPGA devices and throughputs of up to 100 Gbit/s on state-of-the-art ASIC technologies.

10G Ethernet MAC IP

The 10G Ethernet MAC (Media Access Control) IP Core is a high-performance, configurable solution designed to facilitate seamless and reliable data communication over 10 Gigabit Ethernet networks

10GBASE-R PHY FPGA IP

The 10GBASE-R PHY FPGA Intellectual Property (IP) core can be used with either Altera FPGA IP for 10G Ethernet MAC or with a customer-developed Ethernet MAC via a standard XGMII interface running at 156.25 Mbps.

10GBASE-R PHY FPGA IP

The 10GBASE-R PHY FPGA Intellectual Property (IP) core can be used with either Altera FPGA IP for 10G Ethernet MAC or with a customer-developed Ethernet MAC via a standard XGMII interface running at 156.25 Mbps.

10GEDEK (10Gbits/s Ethernet Data Exchange Kit) IP Core

10G Ethernet processor-less stack

10M/100M/1G/10G/25G High capacity Ethernet TSN Switch

The 10M/100M/1G/10G/25G/100G Ethernet Switching IP is an advanced Ethernet Switch IP with an extensive set of QoS features, statistics and Time Sensitive Networking (TSN) capabilities.

1G Deep Buffering Memory Ethernet Switch

make it even shorter12:18 PMClaude responded: Comcores' 1G Deep Buffering Ethernet Switch IP offers external RAM buffering, fine-grained traffic prioritization, and per-port/queue egress shaping, with supp…Comcores' 1G Deep Buffering Ethernet Switch IP offers external RAM buffering, fine-grained traffic prioritization, and per-port/queue egress shaping, with support for MAC learning, VLAN 802.1Q, multicast, and IEEE 1588 transparency

1G/10Gb Ethernet PHY FPGA IP

The 1G/10G Ethernet PHY Altera FPGA Intellectual Property (IP) core supports functionality of both the standard physical coding sublayer (PCS) and the higher data rate 10G PCS with an appropriate physical medium attachment (PMA). 

4G LTE/LTE-A CTC

Creonic’s LTE/LTE-A IP core is an advanced, customer proven implementation of the standardized 3GPP turbo code.